ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
Public Member Functions | List of all members
MWBMemory Class Reference

Simulation ready configurable Wishbone slave memory. More...

#include <memory.h>

Inheritance diagram for MWBMemory:
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Collaboration diagram for MWBMemory:
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Public Member Functions

 MWBMemory (const sc_module_name &name, TWord base, TWord size)
 Create a Wishbone slave memory. More...
 
void SetDelays (uint rd_setup, uint rd_delay, uint wr_setup, uint wr_delay)
 Set read and write setup and delay clock cycles. More...
 
void MainThread ()
 Main SC_THREAD implements the Wishbone slave interface. More...
 
- Public Member Functions inherited from MPeripheral
 MPeripheral (const sc_module_name &name)
 Constructor. More...
 
void Trace (sc_trace_file *tf, int level=1)
 Trace function definition. More...
 
- Public Member Functions inherited from CMemory
 CMemory ()
 
 CMemory (TWord base, TWord size)
 
 ~CMemory ()
 
void Init (TWord base, TWord size)
 
bool IsAdressed (TWord adr)
 
TByte ReadByte (TWord adr)
 
THalfWord ReadHalfWord (TWord adr)
 
TWord ReadWord (TWord adr)
 
TDWord ReadDWord (TWord adr)
 
void WriteByte (TWord adr, TByte val)
 
void WriteHalfWord (TWord adr, THalfWord val)
 
void WriteWord (TWord adr, TWord val)
 
void WriteDWord (TWord adr, TDWord val)
 
bool ReadFile (const char *filename, const bool dumpVHDL)
 
int FindLabel (TWord adr)
 
char * GetDumpStr (TWord adr)
 
char * GetDumpStrVHDL (TWord adr)
 
void Dump (TWord adr0=0, TWord adr1=0xffffffff)
 
void DumpVHDL (const char *filename, unsigned size)
 
void DumpSignature (const char *filename)
 

Additional Inherited Members

- Public Attributes inherited from MPeripheral
sc_in_clk wb_clk_i
 WB Clock input. More...
 
sc_in< bool > wb_rst_i
 WB Reset input. More...
 
sc_in< bool > wb_stb_i
 WB Strobe input. More...
 
sc_in< bool > wb_cyc_i
 WB cycle valid input. More...
 
sc_in< bool > wb_we_i
 WB write enable intput. More...
 
sc_in< sc_uint< 3 > > wb_cti_i
 WB cycle type identifier (optional, for registered feedback). More...
 
sc_in< sc_uint< 2 > > wb_bte_i
 WB burst type extension (optional, for registered feedback). More...
 
sc_in< sc_uint< WB_PORT_SIZE/8 > > wb_sel_i
 WB byte select inputs. More...
 
sc_out< bool > wb_ack_o
 WB normal termination. More...
 
sc_out< bool > wb_err_o
 WB termination w/ error (optional). More...
 
sc_out< bool > wb_rty_o
 WB termination w/ retry (optional). More...
 
sc_in< sc_uint< 32 > > wb_adr_i
 WB address bus inputs. More...
 
sc_in< sc_uint< WB_PORT_SIZE > > wb_dat_i
 WB input data bus. More...
 
sc_out< sc_uint< WB_PORT_SIZE > > wb_dat_o
 WB output data bus. More...
 
- Public Attributes inherited from CMemory
TWord tdata_adr
 
TWord tohost_adr
 
- Protected Attributes inherited from CMemory
TBytedata_
 
TWord base_
 
TWord size_
 
std::vector< CLabellabel_list_
 
bool sig_found_
 
TWord sig_adr_
 
TWord sig_adr_end_
 

Detailed Description

Simulation ready configurable Wishbone slave memory.

This class defines a memory with a Wishbone slave interface and all other necessary functionality to add it to a ParaNut systems Wishbone interconnect (MInterconnect).

It is not synthesizable but rather focusses on functionality to control its behaviour and data during SystemC simulation.

Derived from MPeripheral and CMemory.

Constructor & Destructor Documentation

◆ MWBMemory()

MWBMemory::MWBMemory ( const sc_module_name &  name,
TWord  base,
TWord  size 
)
inline

Create a Wishbone slave memory.

Reserves memory of size, sets it to 0 and sets internal base address to base by calling CMemory() constructor. Sets defaults for the simulation timing members (see SetDelays()) and initialize the SC_THREAD for MainThread().

Parameters
nameis the module name.
baseis the memory base address in the ParaNut system.
sizeis the memory size in byte.

Member Function Documentation

◆ MainThread()

void MWBMemory::MainThread ( )

Main SC_THREAD implements the Wishbone slave interface.

Implements the Wishbone slave to CMemory interace. Is a SC_THREAD for easier setup and delay realisation.

◆ SetDelays()

void MWBMemory::SetDelays ( uint  rd_setup,
uint  rd_delay,
uint  wr_setup,
uint  wr_delay 
)

Set read and write setup and delay clock cycles.

Set internal variables for read and write setup clocks (time from request to first acknowledge) and delay clocks for bursts (time between last and next acknowledge).

Note
The delay is currently disabled and not applied during bursts!
Parameters
rd_setupis the amount of clocks between request and first acknowledge during read.
rd_delayis the amount of clocks between last and next acknowledge during burst read.
wr_setupis the amount of clocks between request and first acknowledge during write.
wr_delayis the amount of clocks between last and next acknowledge during burst write.

The documentation for this class was generated from the following files: