ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
dm.h
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1 /*************************************************************************
2 
3  This file is part of the ParaNut project.
4 
5  Copyright (C) 2019 Alexander Bahle <alexander.bahle@hs-augsburg.de>
6  Hochschule Augsburg, University of Applied Sciences
7 
8  Description:
9  This is a SystemC model of a Debug Module compatible with the
10  RISC-V External Debug Support Version 0.13
11 
12  Redistribution and use in source and binary forms, with or without modification,
13  are permitted provided that the following conditions are met:
14 
15  1. Redistributions of source code must retain the above copyright notice, this
16  list of conditions and the following disclaimer.
17 
18  2. Redistributions in binary form must reproduce the above copyright notice,
19  this list of conditions and the following disclaimer in the documentation and/or
20  other materials provided with the distribution.
21 
22  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
23  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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27  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 
33  *************************************************************************/
34 
35 
36 #ifndef _DM_
37 #define _DM_
38 
39 #include "base.h"
40 #include "paranut-config.h"
41 
42 #include <systemc.h>
43 
44 // **************** Defines *************
45 #define DTM_ADDR_WIDTH 6
46 #define DTM_IR_WIDTH 5
47 
48 #define DBG_CMD_WIDTH 32
49 #define DBG_ADDRESS 0x00000000
50 
51 #define DBG_REG_OFFSET 0x0
52 #define DBG_REG_SIZE 0x40
53 #define DBG_NUM_DATA 1 // Number of 32 bit registers
54 #define DBG_NUM_PROGBUF 3 // Number of 32 bit registers
55 
56 #define DBG_FLAG_OFFSET 0x100
57 #define DBG_FLAG_SIZE CFG_NUT_CPU_CORES // One byte per CPU
58 #define DBG_FLAG_REG_OFFSET 0x10
59 
60 #define DBG_ABSTRACT_OFFSET 0x200
61 #define DBG_ABSTRACT_REG_OFFSET (DBG_NUM_DATA + DBG_NUM_PROGBUF)
62 #define DBG_ABSTRACT_NUM_LD 1
63 #define DBG_ABSTRACT_NUM (1 << DBG_ABSTRACT_NUM_LD)
64 #define DBG_PROGBUF_JUMP (DBG_ABSTRACT_OFFSET + (DBG_ABSTRACT_NUM-1)*4 - DBG_NUM_DATA*4)
65 
66 #define DBG_HALTED_OFFSET 0x300
67 #define DBG_GOING_OFFSET 0x304
68 #define DBG_RESUMING_OFFSET 0x308
69 #define DBG_EXCEPTION_OFFSET 0x30C
70 
71 #define DBG_MEMORY_OFFSET 0x400
72 #define DBG_MEMORY_SIZE 0x54
73 #define DBG_ROM_ADDRESS (DBG_ADDRESS + DBG_MEMORY_OFFSET)
74 
75 #define DBG_NUM_REGISTERS (DBG_NUM_DATA + DBG_NUM_PROGBUF + DBG_ABSTRACT_NUM )
76 #define DBG_NUM_REGISTES_BITS 3 // log2(DBG_NUM_REGISTERS)
77 
78 #define REG_RD_WR_STAGES 3
79 #define REG_STAGES 2
80 #define REG_ID_LAST 1
81 
82 // **************** DM Register Addresses *************
83 typedef enum {
84  data0 = 0x4,
85 
86  dmcontrol = 0x10,
87  dmstatus = 0x11,
88 
89  abstracts = 0x16,
90  command = 0x17,
91  abstractauto = 0x18,
92 
93  progbuf0 = 0x20,
96  progbuf15 = 0x2f,
97 
98  haltsum0 = 0x40,
100 
101 typedef enum {
103 
107 
110 } EDMRegs;
111 
112 // **************** DM Command Error Codes *************
113 typedef enum {
120 } ECMDErr;
121 
122 // **************** DM States *************
123 typedef enum {
129 } EDMState;
130 
131 
132 // **************** MDebugModule *************
133 class MDebugModule : ::sc_core::sc_module {
134 public:
135 
136  // Ports (WISHBONE slave)...
137  sc_in_clk clk_i; // clock input
138  sc_in<bool> rst_i; // reset
139 
140  sc_in<bool> stb_i; // strobe input
141  sc_in<bool> cyc_i; // cycle valid input
142  sc_in<bool> we_i; // indicates write transfer
143  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > sel_i; // byte select inputs
144  sc_out<bool> ack_o; // normal termination
145  sc_out<bool> err_o; // termination w/ error
146  sc_out<bool> rty_o; // termination w/ retry
147 
148  sc_in<sc_uint<32> > adr_i; // address bus inputs
149  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dat_i; // input data bus
150  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dat_o; // output data bus
151 
152  // to EXU
153  // Debug request: EXUs jump to DBG_ROM_ADDRESS upon handling this signal
154  sc_out<sc_uint<CFG_NUT_CPU_CORES> > dbg_request;
155  // Debug reset: Gets set through the ndmreset bit of dmcontrol register and
156  // resets all modules (except DM and DTM)
157  sc_out<bool> dbg_reset;
158 
159  // from DTM
160  sc_in<sc_uint<DTM_ADDR_WIDTH> > dmi_adr_i;
161  sc_in<sc_uint<32> > dmi_dat_i;
162  sc_out<sc_uint<32> > dmi_dat_o;
163  sc_in<bool> dmi_rd,
165 
166  // Constructor...
167  SC_HAS_PROCESS (MDebugModule);
168  MDebugModule (sc_module_name name)
169  : sc_module (name) {
170  SC_METHOD (TransitionMethod);
171  sensitive << dm_state << command_written
174  << haltsum << cmd
175  << wb_ack_o << stb_i << cyc_i;
176 
177  SC_METHOD (RegisterMethod);
178  sensitive << clk_i.pos ();
179  }
180 
181 
182  // Functions...
183  void Trace (sc_trace_file *tf, int levels = 1);
184  static inline bool IsAdressed (TWord adr) { return (adr & 0xffff0000) == DBG_ADDRESS; }
185 
186 #ifndef __SYNTHESIS__
187  void SetNdmreset(bool val) { dmcontrol_ndmreset = val; }
188  void SetHaltreq(bool val) { dmcontrol_haltreq = val; }
189 #endif
190 
191  // Processes...
192  void TransitionMethod ();
193  void RegisterMethod ();
194 
195 protected:
196  // Registers ...
197  sc_signal<sc_uint<3> >
200  sc_signal<bool>
203  sc_signal<sc_uint<32> > dmi_dat_i_last[REG_STAGES];
204  sc_signal<sc_uint<DTM_ADDR_WIDTH> > dmi_adr_last[REG_STAGES];
205 
206  sc_signal<sc_uint<32> > dm_regs[DBG_NUM_REGISTERS];
207  sc_signal<sc_uint<8> > dm_flags[CFG_NUT_CPU_CORES];
208 
209  // dmcontrol:
210  sc_signal<sc_uint<MIN(MAX(CFG_NUT_CPU_CORES_LD, 1), 20)> > dmcontrol_hartsel;
211  sc_signal<bool>
215 
216  // dmstatus:
217  sc_signal<bool>
220 
221  // abstracts:
222  sc_signal<bool>
225  sc_signal<sc_uint<3> >
228 
229  // abstractauto
230  sc_signal<bool> abstractauto_autoexecdata;
231 
232  // haltsum0: // todo: add measures for more than 32 cores
233  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > haltsum;
234 
235  // commmand:
236  sc_signal<sc_uint<32> > cmd;
237 
238 
239  // Internal signals ...
240  sc_signal<bool>
244  sc_signal<sc_uint<DBG_ABSTRACT_NUM_LD> > reg_sel;
245  sc_signal<bool> reg_write;
246  sc_signal<sc_uint<32> > reg_in;
247 
248 };
249 
250 
251 #endif
Helpers, Makros and performance measuring Classes used in most ParaNut files.
Definition: dm.h:133
void SetHaltreq(bool val)
Definition: dm.h:188
sc_signal< bool > dmstatus_allresumeack
Definition: dm.h:219
sc_in< bool > dmi_wr
Definition: dm.h:164
sc_signal< bool > reg_write
Definition: dm.h:245
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > haltsum
Definition: dm.h:233
sc_out< sc_uint< CFG_NUT_CPU_CORES > > dbg_request
Definition: dm.h:154
sc_out< bool > rty_o
Definition: dm.h:146
sc_signal< bool > reg_abstracts_busy
Definition: dm.h:224
void SetNdmreset(bool val)
Definition: dm.h:187
sc_signal< bool > flag_go
Definition: dm.h:242
sc_in< sc_uint< 32 > > adr_i
Definition: dm.h:148
sc_signal< sc_uint< 3 > > abstracts_cmderr
Definition: dm.h:226
void TransitionMethod()
Definition: dm.cpp:105
sc_in< bool > cyc_i
Definition: dm.h:141
sc_signal< bool > command_written
Definition: dm.h:241
void RegisterMethod()
Definition: dm.cpp:234
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > sel_i
Definition: dm.h:143
void Trace(sc_trace_file *tf, int levels=1)
Definition: dm.cpp:37
sc_signal< bool > wb_ack_o
Definition: dm.h:243
sc_in_clk clk_i
Definition: dm.h:137
sc_out< bool > dbg_reset
Definition: dm.h:157
sc_signal< sc_uint< 3 > > dm_state_next
Definition: dm.h:199
sc_signal< sc_uint< DBG_ABSTRACT_NUM_LD > > reg_sel
Definition: dm.h:244
static bool IsAdressed(TWord adr)
Definition: dm.h:184
sc_in< sc_uint< DTM_ADDR_WIDTH > > dmi_adr_i
Definition: dm.h:160
sc_signal< sc_uint< MIN(MAX(CFG_NUT_CPU_CORES_LD, 1), 20)> > dmcontrol_hartsel
Definition: dm.h:210
sc_signal< sc_uint< 3 > > dm_state
Definition: dm.h:198
sc_signal< bool > dmi_rd_last[REG_RD_WR_STAGES]
Definition: dm.h:202
sc_signal< sc_uint< 3 > > reg_abstracts_cmderr
Definition: dm.h:227
sc_in< bool > dmi_rd
Definition: dm.h:163
sc_in< bool > we_i
Definition: dm.h:142
sc_signal< bool > dmcontrol_ndmreset
Definition: dm.h:214
sc_signal< bool > dmcontrol_active
Definition: dm.h:213
sc_signal< sc_uint< 32 > > dmi_dat_i_last[REG_STAGES]
Definition: dm.h:203
sc_signal< sc_uint< 8 > > dm_flags[CFG_NUT_CPU_CORES]
Definition: dm.h:207
sc_signal< bool > abstractauto_autoexecdata
Definition: dm.h:230
sc_signal< sc_uint< DTM_ADDR_WIDTH > > dmi_adr_last[REG_STAGES]
Definition: dm.h:204
sc_signal< bool > dmcontrol_haltreq
Definition: dm.h:212
sc_signal< sc_uint< 32 > > reg_in
Definition: dm.h:246
sc_out< bool > ack_o
Definition: dm.h:144
sc_in< bool > rst_i
Definition: dm.h:138
sc_signal< bool > dmstatus_allhalted
Definition: dm.h:218
sc_signal< sc_uint< 32 > > cmd
Definition: dm.h:236
sc_out< bool > err_o
Definition: dm.h:145
sc_signal< sc_uint< 32 > > dm_regs[DBG_NUM_REGISTERS]
Definition: dm.h:206
sc_out< sc_uint< 32 > > dmi_dat_o
Definition: dm.h:162
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_o
Definition: dm.h:150
sc_signal< bool > dmi_wr_last[REG_RD_WR_STAGES]
Definition: dm.h:201
sc_in< bool > stb_i
Definition: dm.h:140
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_i
Definition: dm.h:149
MDebugModule(sc_module_name name)
Definition: dm.h:168
sc_signal< bool > abstracts_busy
Definition: dm.h:223
sc_in< sc_uint< 32 > > dmi_dat_i
Definition: dm.h:161
#define DBG_ADDRESS
Definition: dm.h:49
#define REG_STAGES
Definition: dm.h:79
#define DBG_NUM_REGISTERS
Definition: dm.h:75
EDMRegs
Definition: dm.h:101
@ reg_data0
Definition: dm.h:102
@ reg_abstract0
Definition: dm.h:108
@ reg_progbuf1
Definition: dm.h:105
@ reg_progbuf2
Definition: dm.h:106
@ reg_abstract1
Definition: dm.h:109
@ reg_progbuf0
Definition: dm.h:104
#define REG_RD_WR_STAGES
Definition: dm.h:78
EDMRegAddress
Definition: dm.h:83
@ progbuf15
Definition: dm.h:96
@ progbuf0
Definition: dm.h:93
@ progbuf1
Definition: dm.h:94
@ haltsum0
Definition: dm.h:98
@ progbuf2
Definition: dm.h:95
@ abstractauto
Definition: dm.h:91
@ data0
Definition: dm.h:84
@ command
Definition: dm.h:90
@ abstracts
Definition: dm.h:89
@ dmcontrol
Definition: dm.h:86
@ dmstatus
Definition: dm.h:87
EDMState
Definition: dm.h:123
@ CMD
Definition: dm.h:125
@ CMD_GO
Definition: dm.h:128
@ CMD_POSTEXEC
Definition: dm.h:127
@ CMD_ACCESSR
Definition: dm.h:126
@ Idle
Definition: dm.h:124
ECMDErr
Definition: dm.h:113
@ CMDERR_EXCEPTION
Definition: dm.h:117
@ CMDERR_NOTSUP
Definition: dm.h:116
@ CMDERR_NONE
Definition: dm.h:114
@ CMDERR_HALTRESUME
Definition: dm.h:118
@ CMDERR_BUSY
Definition: dm.h:115
@ CMDERR_OTHER
Definition: dm.h:119
#define CFG_NUT_CPU_CORES
Number of cores overall (derived).
Definition: paranut-config.h:98
#define CFG_NUT_CPU_CORES_LD
Number of cores overall as log2.
Definition: paranut-config.h:96
#define CFG_MEMU_BUSIF_WIDTH
Busif Data Width.
Definition: paranut-config.h:228
unsigned TWord
Word type (32 Bit).
Definition: base.h:147
#define MAX(A, B)
Maximum of A and B.
Definition: base.h:154
#define MIN(A, B)
Minimum of A and B.
Definition: base.h:152
Configuration Makros used in most ParaNut files.
sc_trace_file * tf
Definition: tlb_tb.cpp:94