#include <memu.h>
◆ MWritePort()
MWritePort::MWritePort |
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sc_module_name |
name | ) |
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inline |
◆ MainMethod()
void MWritePort::MainMethod |
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◆ Trace()
void MWritePort::Trace |
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sc_trace_file * |
tf, |
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int |
level = 1 |
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) |
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◆ TransitionMethod()
void MWritePort::TransitionMethod |
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◆ bank_bsel
sc_out<sc_uint<4> > MWritePort::bank_bsel |
◆ bank_data_in
sc_in<sc_uint<32> > MWritePort::bank_data_in |
◆ bank_data_out
sc_out<sc_uint<32> > MWritePort::bank_data_out |
◆ bank_rd
sc_out<bool> MWritePort::bank_rd |
◆ bank_wr
sc_out<bool> MWritePort::bank_wr |
◆ busif_ac_w
sc_in<bool> MWritePort::busif_ac_w |
◆ busif_adr
sc_in<sc_uint<32> > MWritePort::busif_adr |
◆ busif_busy
sc_in<bool> MWritePort::busif_busy |
◆ busif_nolinelock
sc_out<bool> MWritePort::busif_nolinelock |
◆ busif_op
◆ clk
sc_in<bool> MWritePort::clk |
◆ data_reg
sc_signal<sc_uint<32> > MWritePort::data_reg |
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protected |
◆ gnt_bank
◆ gnt_busif
sc_in<bool> MWritePort::gnt_busif |
◆ gnt_linelock
sc_in<bool> MWritePort::gnt_linelock |
◆ gnt_tagr
sc_in<bool> MWritePort::gnt_tagr |
◆ gnt_tagw
sc_in<bool> MWritePort::gnt_tagw |
◆ next_data_reg
sc_signal<sc_uint<32> > MWritePort::next_data_reg |
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protected |
◆ next_state
◆ next_tag_reg
sc_signal<SCacheTag> MWritePort::next_tag_reg |
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protected |
◆ port_ac_w
sc_out<bool> MWritePort::port_ac_w |
◆ port_ack
sc_out<bool> MWritePort::port_ack |
◆ port_adr
sc_in<sc_uint<32> > MWritePort::port_adr |
◆ port_bsel
sc_in<sc_uint<4> > MWritePort::port_bsel |
◆ port_cache_op
sc_in<sc_uint<3> > MWritePort::port_cache_op |
◆ port_data
sc_in<sc_uint<32> > MWritePort::port_data |
◆ port_direct
sc_in<bool> MWritePort::port_direct |
◆ port_lres_scond
sc_in<bool> MWritePort::port_lres_scond |
◆ port_scond_ok
sc_in<bool> MWritePort::port_scond_ok |
◆ port_trap_no_u
sc_in<bool> MWritePort::port_trap_no_u |
◆ port_trap_u
sc_in<bool> MWritePort::port_trap_u |
◆ port_wr
sc_in<bool> MWritePort::port_wr |
◆ req_bank
◆ req_busif
sc_out<bool> MWritePort::req_busif |
◆ req_linelock
sc_out<bool> MWritePort::req_linelock |
◆ req_tagr
sc_out<bool> MWritePort::req_tagr |
◆ req_tagw
sc_out<bool> MWritePort::req_tagw |
◆ reset
sc_in<bool> MWritePort::reset |
◆ state_reg
◆ state_trace
sc_signal<int> MWritePort::state_trace |
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protected |
◆ tag_in
◆ tag_out
◆ tag_rd
sc_out<bool> MWritePort::tag_rd |
◆ tag_reg
◆ tag_wr
sc_out<bool> MWritePort::tag_wr |
The documentation for this class was generated from the following files: