ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
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Class containing the interface for Wishbone slave peripherals. More...
#include <paranut-peripheral.h>
Public Member Functions | |
MPeripheral (const sc_module_name &name) | |
Constructor. More... | |
void | Trace (sc_trace_file *tf, int level=1) |
Trace function definition. More... | |
Public Attributes | |
Wishbone slave ports... | |
sc_in_clk | wb_clk_i |
WB Clock input. More... | |
sc_in< bool > | wb_rst_i |
WB Reset input. More... | |
sc_in< bool > | wb_stb_i |
WB Strobe input. More... | |
sc_in< bool > | wb_cyc_i |
WB cycle valid input. More... | |
sc_in< bool > | wb_we_i |
WB write enable intput. More... | |
sc_in< sc_uint< 3 > > | wb_cti_i |
WB cycle type identifier (optional, for registered feedback). More... | |
sc_in< sc_uint< 2 > > | wb_bte_i |
WB burst type extension (optional, for registered feedback). More... | |
sc_in< sc_uint< WB_PORT_SIZE/8 > > | wb_sel_i |
WB byte select inputs. More... | |
sc_out< bool > | wb_ack_o |
WB normal termination. More... | |
sc_out< bool > | wb_err_o |
WB termination w/ error (optional). More... | |
sc_out< bool > | wb_rty_o |
WB termination w/ retry (optional). More... | |
sc_in< sc_uint< 32 > > | wb_adr_i |
WB address bus inputs. More... | |
sc_in< sc_uint< WB_PORT_SIZE > > | wb_dat_i |
WB input data bus. More... | |
sc_out< sc_uint< WB_PORT_SIZE > > | wb_dat_o |
WB output data bus. More... | |
Class containing the interface for Wishbone slave peripherals.
Defines the Wishbone input and output ports necessary to connect a peripheral to the simulation Wishbone interconnect (MInterconnect)
Has no other functionality (no Methods or Threads).
Can be used as base class for for simulation only peripherals (see MWBMemory for example).
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inline |
Constructor.
Does nothing except for naming all the ports for easier elaboration time debugging.
name | is the module name. |
void MPeripheral::Trace | ( | sc_trace_file * | tf, |
int | level = 1 |
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Trace function definition.
Does nothing, but when overridden in a child should add internal signals/registers and ports to the trace file tf. The trace level is only necessary for peripherals with submodules.
tf | is the sc_trace_file to where to add everything. |
level | is the trace level (for submodules). |
sc_out<bool> MPeripheral::wb_ack_o |
WB normal termination.
sc_in<sc_uint<32> > MPeripheral::wb_adr_i |
WB address bus inputs.
sc_in<sc_uint<2> > MPeripheral::wb_bte_i |
WB burst type extension (optional, for registered feedback).
sc_in_clk MPeripheral::wb_clk_i |
WB Clock input.
sc_in<sc_uint<3> > MPeripheral::wb_cti_i |
WB cycle type identifier (optional, for registered feedback).
sc_in<bool> MPeripheral::wb_cyc_i |
WB cycle valid input.
sc_in<sc_uint<WB_PORT_SIZE> > MPeripheral::wb_dat_i |
WB input data bus.
sc_out<sc_uint<WB_PORT_SIZE> > MPeripheral::wb_dat_o |
WB output data bus.
sc_out<bool> MPeripheral::wb_err_o |
WB termination w/ error (optional).
sc_in<bool> MPeripheral::wb_rst_i |
WB Reset input.
sc_out<bool> MPeripheral::wb_rty_o |
WB termination w/ retry (optional).
sc_in<sc_uint<WB_PORT_SIZE/8> > MPeripheral::wb_sel_i |
WB byte select inputs.
sc_in<bool> MPeripheral::wb_stb_i |
WB Strobe input.
sc_in<bool> MPeripheral::wb_we_i |
WB write enable intput.