ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
Public Member Functions | Public Attributes | Protected Member Functions | Protected Attributes | List of all members
MMemu Class Reference

#include <memu.h>

Inheritance diagram for MMemu:
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Collaboration diagram for MMemu:
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Public Member Functions

 MMemu (sc_module_name name)
 
 ~MMemu ()
 
void Trace (sc_trace_file *tf, int levels=1)
 
void TransitionMethod ()
 
void InterconnectMethod ()
 

Public Attributes

sc_in< bool > clk
 
sc_in< bool > reset
 
sc_out< bool > wb_cyc_o
 
sc_out< bool > wb_stb_o
 
sc_out< bool > wb_we_o
 
sc_out< sc_uint< 3 > > wb_cti_o
 
sc_out< sc_uint< 2 > > wb_bte_o
 
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > wb_sel_o
 
sc_out< sc_uint< 32 > > wb_adr_o
 
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_o
 
sc_in< bool > wb_ack_i
 
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_i
 
sc_in< bool > rp_rd [CFG_MEMU_RPORTS]
 
sc_in< bool > rp_direct [CFG_MEMU_RPORTS]
 
sc_in< sc_uint< 4 > > rp_bsel [CFG_MEMU_RPORTS]
 
sc_in< bool > rp_paging [CFG_MEMU_RPORTS]
 
sc_out< bool > rp_ack [CFG_MEMU_RPORTS]
 
sc_in< sc_uint< 32 > > rp_adr [CFG_MEMU_RPORTS]
 
sc_out< sc_uint< 32 > > rp_data [CFG_MEMU_RPORTS]
 
sc_out< bool > rp_ac_r [CFG_MEMU_RPORTS]
 
sc_out< bool > rp_ac_x [CFG_MEMU_RPORTS]
 
sc_out< bool > rp_ac_u [CFG_MEMU_RPORTS]
 
sc_in< bool > wp_wr [CFG_MEMU_WPORTS]
 
sc_in< bool > wp_direct [CFG_MEMU_WPORTS]
 
sc_in< sc_uint< 4 > > wp_bsel [CFG_MEMU_WPORTS]
 
sc_in< bool > wp_paging [CFG_MEMU_WPORTS]
 
sc_out< bool > wp_ack [CFG_MEMU_WPORTS]
 
sc_in< bool > wp_lres_scond [CFG_MEMU_WPORTS]
 
sc_out< bool > wp_scond_ok [CFG_MEMU_WPORTS]
 
sc_in< sc_uint< 3 > > wp_cache_op [CFG_MEMU_WPORTS]
 
sc_in< sc_uint< 32 > > wp_adr [CFG_MEMU_WPORTS]
 
sc_in< sc_uint< 32 > > wp_data [CFG_MEMU_WPORTS]
 
sc_out< bool > wp_ac_w [CFG_MEMU_WPORTS]
 
sc_in< bool > wp_trap_u [CFG_MEMU_WPORTS]
 
sc_in< bool > wp_trap_no_u [CFG_MEMU_WPORTS]
 
sc_in< sc_uint< 20 > > root_ppn
 
sc_in< bool > tlb_flush
 
MTagRamtagRam
 
MBankRambankRam [CFG_MEMU_CACHE_BANKS]
 
MBusController * busController
 
MBusIfbusIf
 
MPtw * ptw
 
MTlbtlb
 
MArbiterarbiter
 
MReadPortreadPorts [CFG_MEMU_RPORTS]
 
MWritePortwritePorts [CFG_MEMU_WPORTS]
 

Protected Member Functions

void InitSubmodules ()
 
void FreeSubmodules ()
 
void InitInterconnectMethod ()
 

Protected Attributes

sc_signal< bool > tagram_ready
 
sc_signal< bool > tagram_rd [TR_PORTS]
 
sc_signal< bool > tagram_wr [TR_PORTS]
 
sc_signal< sc_uint< 32 > > tagram_adr [TR_PORTS]
 
sc_signal< sc_uint< 32 > > tagram_wadr [TR_PORTS]
 
sc_signal< SCacheTagtagram_tag_in [TR_PORTS]
 
sc_signal< SCacheTagtagram_tag_out [TR_PORTS]
 
sc_signal< bool > bankram_rd [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
 
sc_signal< bool > bankram_wr [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
 
sc_signal< sc_uint< 4 > > bankram_wen [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
 
sc_signal< sc_uint< 32 > > bankram_wiadr [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
 
sc_signal< sc_uint< 32 > > bankram_wdata [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
 
sc_signal< sc_uint< 32 > > bankram_rdata [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
 
sc_signal< bool > master_cyc [MASTER_NO]
 
sc_signal< bool > master_stb [MASTER_NO]
 
sc_signal< bool > master_we [MASTER_NO]
 
sc_signal< sc_uint< 3 > > master_cti [MASTER_NO]
 
sc_signal< sc_uint< 2 > > master_bte [MASTER_NO]
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > master_sel [MASTER_NO]
 
sc_signal< sc_uint< 32 > > master_adr [MASTER_NO]
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > master_dat [MASTER_NO]
 
sc_signal< bool > switch_master
 
sc_signal< EBusIfOperationbusif_op
 
sc_signal< bool > busif_nolinelock
 
sc_signal< bool > busif_busy
 
sc_signal< bool > busif_tag_rd
 
sc_signal< bool > busif_tag_rd_way
 
sc_signal< bool > busif_tag_wr
 
sc_signal< bool > busif_bank_rd [CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > busif_bank_wr [CFG_MEMU_CACHE_BANKS]
 
sc_signal< sc_uint< 32 > > busif_adr_in
 
sc_signal< sc_uint< 32 > > busif_adr_out
 
sc_signal< sc_uint< 32 > > busif_data_in [CFG_MEMU_CACHE_BANKS]
 
sc_signal< sc_uint< 32 > > busif_data_out [CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > busif_data_out_valid [CFG_MEMU_CACHE_BANKS]
 
sc_signal< SCacheTagbusif_tag_in
 
sc_signal< SCacheTagbusif_tag_out
 
sc_signal< sc_uint< 4 > > busif_bsel
 
sc_signal< bool > busif_ac_r
 
sc_signal< bool > busif_ac_w
 
sc_signal< bool > busif_ac_x
 
sc_signal< bool > busif_ac_u
 
sc_signal< bool > busif_trap_u
 
sc_signal< bool > busif_trap_no_u
 
sc_signal< bool > busif_paging
 
sc_signal< sc_uint< 32 > > rp_busif_data_reg [CFG_MEMU_BUSIF_WIDTH/32]
 
sc_signal< sc_uint< 32 > > rp_busif_data [CFG_MEMU_RPORTS]
 
sc_signal< EBusIfOperationrp_busif_op [CFG_MEMU_RPORTS]
 
sc_signal< bool > rp_tag_rd [CFG_MEMU_RPORTS]
 
sc_signal< bool > rp_bank_rd [CFG_MEMU_RPORTS]
 
sc_signal< SCacheTagrp_tag_in [CFG_MEMU_RPORTS]
 
sc_signal< sc_uint< 32 > > rp_way_out [CFG_MEMU_RPORTS]
 
sc_signal< sc_uint< 32 > > rp_bank_data_in [CFG_MEMU_RPORTS]
 
sc_signal< sc_uint< 32 > > rp_bank_sel [CFG_MEMU_RPORTS]
 
sc_signal< EBusIfOperationwp_busif_op [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_busif_nolinelock [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_tag_rd [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_tag_wr [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_bank_rd [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_bank_wr [CFG_MEMU_WPORTS]
 
sc_signal< SCacheTagwp_tag_in [CFG_MEMU_WPORTS]
 
sc_signal< SCacheTagwp_tag_out [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 32 > > wp_bank_data_in [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 32 > > wp_bank_data_out [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 4 > > wp_bank_bsel [CFG_MEMU_WPORTS]
 
sc_signal< bool > req_busif_linelock
 
sc_signal< bool > req_wp_linelock [CFG_MEMU_WPORTS]
 
sc_signal< bool > gnt_busif_linelock
 
sc_signal< bool > gnt_wp_linelock [CFG_MEMU_WPORTS]
 
sc_signal< bool > req_busif_tagw
 
sc_signal< bool > req_wp_tagw [CFG_MEMU_WPORTS]
 
sc_signal< bool > req_busif_tagr
 
sc_signal< bool > req_wp_tagr [CFG_MEMU_WPORTS]
 
sc_signal< bool > req_rp_tagr [CFG_MEMU_RPORTS]
 
sc_signal< bool > gnt_busif_tagw
 
sc_signal< bool > gnt_wp_tagw [CFG_MEMU_WPORTS]
 
sc_signal< bool > gnt_busif_tagr
 
sc_signal< bool > gnt_wp_tagr [CFG_MEMU_WPORTS]
 
sc_signal< bool > gnt_rp_tagr [CFG_MEMU_RPORTS]
 
sc_signal< bool > gnt_busif_tagw_r
 
sc_signal< bool > gnt_wp_tagw_r [CFG_MEMU_WPORTS]
 
sc_signal< bool > gnt_busif_tagr_r
 
sc_signal< bool > gnt_wp_tagr_r [CFG_MEMU_WPORTS]
 
sc_signal< bool > gnt_rp_tagr_r [CFG_MEMU_RPORTS]
 
sc_signal< bool > req_busif_bank [CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > req_wp_bank [CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > req_rp_bank [CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > gnt_busif_bank [CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > gnt_wp_bank [CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > gnt_rp_bank [CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
 
sc_signal< bool > req_rp_busif [CFG_MEMU_RPORTS]
 
sc_signal< bool > gnt_rp_busif [CFG_MEMU_RPORTS]
 
sc_signal< bool > req_wp_busif [CFG_MEMU_WPORTS]
 
sc_signal< bool > gnt_wp_busif [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 32 > > wiadr_busif
 
sc_signal< sc_uint< 32 > > wiadr_rp [CFG_MEMU_RPORTS]
 
sc_signal< sc_uint< 32 > > adr_wp [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 32 > > way_wp [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 32 > > snoop_adr
 
sc_signal< bool > snoop_stb [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 32 > > ptw_phys_adr
 
sc_signal< sc_uint< 32 > > ptw_virt_adr
 
sc_signal< bool > ptw_req
 
sc_signal< bool > ptw_ack
 
sc_signal< bool > ptw_ac_r
 
sc_signal< bool > ptw_ac_w
 
sc_signal< bool > ptw_ac_x
 
sc_signal< bool > ptw_ac_u
 
sc_signal< bool > ptw_ac_d
 
sc_signal< bool > ptw_ac_a
 
sc_signal< bool > tlb_req
 
sc_signal< bool > tlb_wr
 
sc_signal< sc_uint< 20 > > tlb_va_o
 
sc_signal< sc_uint< 20 > > tlb_pa_o
 
sc_signal< bool > tlb_superpage_o
 
sc_signal< bool > tlb_ac_r_o
 
sc_signal< bool > tlb_ac_w_o
 
sc_signal< bool > tlb_ac_x_o
 
sc_signal< bool > tlb_ac_u_o
 
sc_signal< bool > tlb_ac_d_o
 
sc_signal< bool > tlb_ac_a_o
 
sc_signal< bool > tlb_superpage_i
 
sc_signal< sc_uint< 20 > > tlb_adr_i
 
sc_signal< bool > tlb_hit
 
sc_signal< bool > tlb_miss
 
sc_signal< bool > tlb_ac_r_i
 
sc_signal< bool > tlb_ac_w_i
 
sc_signal< bool > tlb_ac_x_i
 
sc_signal< bool > tlb_ac_u_i
 
sc_signal< bool > tlb_ac_d_i
 
sc_signal< bool > tlb_ac_a_i
 

Constructor & Destructor Documentation

◆ MMemu()

MMemu::MMemu ( sc_module_name  name)
inline

◆ ~MMemu()

MMemu::~MMemu ( )
inline

Member Function Documentation

◆ FreeSubmodules()

void MMemu::FreeSubmodules ( )
protected

◆ InitInterconnectMethod()

void MMemu::InitInterconnectMethod ( )
protected

◆ InitSubmodules()

void MMemu::InitSubmodules ( )
protected

◆ InterconnectMethod()

void MMemu::InterconnectMethod ( )

◆ Trace()

void MMemu::Trace ( sc_trace_file *  tf,
int  levels = 1 
)

◆ TransitionMethod()

void MMemu::TransitionMethod ( )

Member Data Documentation

◆ adr_wp

sc_signal<sc_uint<32> > MMemu::adr_wp[CFG_MEMU_WPORTS]
protected

◆ arbiter

MArbiter* MMemu::arbiter

◆ bankRam

MBankRam* MMemu::bankRam[CFG_MEMU_CACHE_BANKS]

◆ bankram_rd

sc_signal<bool> MMemu::bankram_rd[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
protected

◆ bankram_rdata

sc_signal<sc_uint<32> > MMemu::bankram_rdata[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
protected

◆ bankram_wdata

sc_signal<sc_uint<32> > MMemu::bankram_wdata[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
protected

◆ bankram_wen

sc_signal<sc_uint<4> > MMemu::bankram_wen[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
protected

◆ bankram_wiadr

sc_signal<sc_uint<32> > MMemu::bankram_wiadr[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
protected

◆ bankram_wr

sc_signal<bool> MMemu::bankram_wr[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
protected

◆ busController

MBusController* MMemu::busController

◆ busIf

MBusIf* MMemu::busIf

◆ busif_ac_r

sc_signal<bool> MMemu::busif_ac_r
protected

◆ busif_ac_u

sc_signal<bool> MMemu::busif_ac_u
protected

◆ busif_ac_w

sc_signal<bool> MMemu::busif_ac_w
protected

◆ busif_ac_x

sc_signal<bool> MMemu::busif_ac_x
protected

◆ busif_adr_in

sc_signal<sc_uint<32> > MMemu::busif_adr_in
protected

◆ busif_adr_out

sc_signal<sc_uint<32> > MMemu::busif_adr_out
protected

◆ busif_bank_rd

sc_signal<bool> MMemu::busif_bank_rd[CFG_MEMU_CACHE_BANKS]
protected

◆ busif_bank_wr

sc_signal<bool> MMemu::busif_bank_wr[CFG_MEMU_CACHE_BANKS]
protected

◆ busif_bsel

sc_signal<sc_uint<4> > MMemu::busif_bsel
protected

◆ busif_busy

sc_signal<bool> MMemu::busif_busy
protected

◆ busif_data_in

sc_signal<sc_uint<32> > MMemu::busif_data_in[CFG_MEMU_CACHE_BANKS]
protected

◆ busif_data_out

sc_signal<sc_uint<32> > MMemu::busif_data_out[CFG_MEMU_CACHE_BANKS]
protected

◆ busif_data_out_valid

sc_signal<bool> MMemu::busif_data_out_valid[CFG_MEMU_CACHE_BANKS]
protected

◆ busif_nolinelock

sc_signal<bool> MMemu::busif_nolinelock
protected

◆ busif_op

sc_signal<EBusIfOperation> MMemu::busif_op
protected

◆ busif_paging

sc_signal<bool> MMemu::busif_paging
protected

◆ busif_tag_in

sc_signal<SCacheTag> MMemu::busif_tag_in
protected

◆ busif_tag_out

sc_signal<SCacheTag> MMemu::busif_tag_out
protected

◆ busif_tag_rd

sc_signal<bool> MMemu::busif_tag_rd
protected

◆ busif_tag_rd_way

sc_signal<bool> MMemu::busif_tag_rd_way
protected

◆ busif_tag_wr

sc_signal<bool> MMemu::busif_tag_wr
protected

◆ busif_trap_no_u

sc_signal<bool> MMemu::busif_trap_no_u
protected

◆ busif_trap_u

sc_signal<bool> MMemu::busif_trap_u
protected

◆ clk

sc_in<bool> MMemu::clk

◆ gnt_busif_bank

sc_signal<bool> MMemu::gnt_busif_bank[CFG_MEMU_CACHE_BANKS]
protected

◆ gnt_busif_linelock

sc_signal<bool> MMemu::gnt_busif_linelock
protected

◆ gnt_busif_tagr

sc_signal<bool> MMemu::gnt_busif_tagr
protected

◆ gnt_busif_tagr_r

sc_signal<bool> MMemu::gnt_busif_tagr_r
protected

◆ gnt_busif_tagw

sc_signal<bool> MMemu::gnt_busif_tagw
protected

◆ gnt_busif_tagw_r

sc_signal<bool> MMemu::gnt_busif_tagw_r
protected

◆ gnt_rp_bank

sc_signal<bool> MMemu::gnt_rp_bank[CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
protected

◆ gnt_rp_busif

sc_signal<bool> MMemu::gnt_rp_busif[CFG_MEMU_RPORTS]
protected

◆ gnt_rp_tagr

sc_signal<bool> MMemu::gnt_rp_tagr[CFG_MEMU_RPORTS]
protected

◆ gnt_rp_tagr_r

sc_signal<bool> MMemu::gnt_rp_tagr_r[CFG_MEMU_RPORTS]
protected

◆ gnt_wp_bank

sc_signal<bool> MMemu::gnt_wp_bank[CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
protected

◆ gnt_wp_busif

sc_signal<bool> MMemu::gnt_wp_busif[CFG_MEMU_WPORTS]
protected

◆ gnt_wp_linelock

sc_signal<bool> MMemu::gnt_wp_linelock[CFG_MEMU_WPORTS]
protected

◆ gnt_wp_tagr

sc_signal<bool> MMemu::gnt_wp_tagr[CFG_MEMU_WPORTS]
protected

◆ gnt_wp_tagr_r

sc_signal<bool> MMemu::gnt_wp_tagr_r[CFG_MEMU_WPORTS]
protected

◆ gnt_wp_tagw

sc_signal<bool> MMemu::gnt_wp_tagw[CFG_MEMU_WPORTS]
protected

◆ gnt_wp_tagw_r

sc_signal<bool> MMemu::gnt_wp_tagw_r[CFG_MEMU_WPORTS]
protected

◆ master_adr

sc_signal<sc_uint<32> > MMemu::master_adr[MASTER_NO]
protected

◆ master_bte

sc_signal<sc_uint<2> > MMemu::master_bte[MASTER_NO]
protected

◆ master_cti

sc_signal<sc_uint<3> > MMemu::master_cti[MASTER_NO]
protected

◆ master_cyc

sc_signal<bool> MMemu::master_cyc[MASTER_NO]
protected

◆ master_dat

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MMemu::master_dat[MASTER_NO]
protected

◆ master_sel

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > MMemu::master_sel[MASTER_NO]
protected

◆ master_stb

sc_signal<bool> MMemu::master_stb[MASTER_NO]
protected

◆ master_we

sc_signal<bool> MMemu::master_we[MASTER_NO]
protected

◆ ptw

MPtw* MMemu::ptw

◆ ptw_ac_a

sc_signal<bool> MMemu::ptw_ac_a
protected

◆ ptw_ac_d

sc_signal<bool> MMemu::ptw_ac_d
protected

◆ ptw_ac_r

sc_signal<bool> MMemu::ptw_ac_r
protected

◆ ptw_ac_u

sc_signal<bool> MMemu::ptw_ac_u
protected

◆ ptw_ac_w

sc_signal<bool> MMemu::ptw_ac_w
protected

◆ ptw_ac_x

sc_signal<bool> MMemu::ptw_ac_x
protected

◆ ptw_ack

sc_signal<bool> MMemu::ptw_ack
protected

◆ ptw_phys_adr

sc_signal<sc_uint<32> > MMemu::ptw_phys_adr
protected

◆ ptw_req

sc_signal<bool> MMemu::ptw_req
protected

◆ ptw_virt_adr

sc_signal<sc_uint<32> > MMemu::ptw_virt_adr
protected

◆ readPorts

MReadPort* MMemu::readPorts[CFG_MEMU_RPORTS]

◆ req_busif_bank

sc_signal<bool> MMemu::req_busif_bank[CFG_MEMU_CACHE_BANKS]
protected

◆ req_busif_linelock

sc_signal<bool> MMemu::req_busif_linelock
protected

◆ req_busif_tagr

sc_signal<bool> MMemu::req_busif_tagr
protected

◆ req_busif_tagw

sc_signal<bool> MMemu::req_busif_tagw
protected

◆ req_rp_bank

sc_signal<bool> MMemu::req_rp_bank[CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
protected

◆ req_rp_busif

sc_signal<bool> MMemu::req_rp_busif[CFG_MEMU_RPORTS]
protected

◆ req_rp_tagr

sc_signal<bool> MMemu::req_rp_tagr[CFG_MEMU_RPORTS]
protected

◆ req_wp_bank

sc_signal<bool> MMemu::req_wp_bank[CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
protected

◆ req_wp_busif

sc_signal<bool> MMemu::req_wp_busif[CFG_MEMU_WPORTS]
protected

◆ req_wp_linelock

sc_signal<bool> MMemu::req_wp_linelock[CFG_MEMU_WPORTS]
protected

◆ req_wp_tagr

sc_signal<bool> MMemu::req_wp_tagr[CFG_MEMU_WPORTS]
protected

◆ req_wp_tagw

sc_signal<bool> MMemu::req_wp_tagw[CFG_MEMU_WPORTS]
protected

◆ reset

sc_in<bool> MMemu::reset

◆ root_ppn

sc_in<sc_uint<20> > MMemu::root_ppn

◆ rp_ac_r

sc_out<bool> MMemu::rp_ac_r[CFG_MEMU_RPORTS]

◆ rp_ac_u

sc_out<bool> MMemu::rp_ac_u[CFG_MEMU_RPORTS]

◆ rp_ac_x

sc_out<bool> MMemu::rp_ac_x[CFG_MEMU_RPORTS]

◆ rp_ack

sc_out<bool> MMemu::rp_ack[CFG_MEMU_RPORTS]

◆ rp_adr

sc_in<sc_uint<32> > MMemu::rp_adr[CFG_MEMU_RPORTS]

◆ rp_bank_data_in

sc_signal<sc_uint<32> > MMemu::rp_bank_data_in[CFG_MEMU_RPORTS]
protected

◆ rp_bank_rd

sc_signal<bool> MMemu::rp_bank_rd[CFG_MEMU_RPORTS]
protected

◆ rp_bank_sel

sc_signal<sc_uint<32> > MMemu::rp_bank_sel[CFG_MEMU_RPORTS]
protected

◆ rp_bsel

sc_in<sc_uint<4> > MMemu::rp_bsel[CFG_MEMU_RPORTS]

◆ rp_busif_data

sc_signal<sc_uint<32> > MMemu::rp_busif_data[CFG_MEMU_RPORTS]
protected

◆ rp_busif_data_reg

sc_signal<sc_uint<32> > MMemu::rp_busif_data_reg[CFG_MEMU_BUSIF_WIDTH/32]
protected

◆ rp_busif_op

sc_signal<EBusIfOperation> MMemu::rp_busif_op[CFG_MEMU_RPORTS]
protected

◆ rp_data

sc_out<sc_uint<32> > MMemu::rp_data[CFG_MEMU_RPORTS]

◆ rp_direct

sc_in<bool> MMemu::rp_direct[CFG_MEMU_RPORTS]

◆ rp_paging

sc_in<bool> MMemu::rp_paging[CFG_MEMU_RPORTS]

◆ rp_rd

sc_in<bool> MMemu::rp_rd[CFG_MEMU_RPORTS]

◆ rp_tag_in

sc_signal<SCacheTag> MMemu::rp_tag_in[CFG_MEMU_RPORTS]
protected

◆ rp_tag_rd

sc_signal<bool> MMemu::rp_tag_rd[CFG_MEMU_RPORTS]
protected

◆ rp_way_out

sc_signal<sc_uint<32> > MMemu::rp_way_out[CFG_MEMU_RPORTS]
protected

◆ snoop_adr

sc_signal<sc_uint<32> > MMemu::snoop_adr
protected

◆ snoop_stb

sc_signal<bool> MMemu::snoop_stb[CFG_MEMU_WPORTS]
protected

◆ switch_master

sc_signal<bool> MMemu::switch_master
protected

◆ tagRam

MTagRam* MMemu::tagRam

◆ tagram_adr

sc_signal<sc_uint<32> > MMemu::tagram_adr[TR_PORTS]
protected

◆ tagram_rd

sc_signal<bool> MMemu::tagram_rd[TR_PORTS]
protected

◆ tagram_ready

sc_signal<bool> MMemu::tagram_ready
protected

◆ tagram_tag_in

sc_signal<SCacheTag> MMemu::tagram_tag_in[TR_PORTS]
protected

◆ tagram_tag_out

sc_signal<SCacheTag> MMemu::tagram_tag_out[TR_PORTS]
protected

◆ tagram_wadr

sc_signal<sc_uint<32> > MMemu::tagram_wadr[TR_PORTS]
protected

◆ tagram_wr

sc_signal<bool> MMemu::tagram_wr[TR_PORTS]
protected

◆ tlb

MTlb* MMemu::tlb

◆ tlb_ac_a_i

sc_signal<bool> MMemu::tlb_ac_a_i
protected

◆ tlb_ac_a_o

sc_signal<bool> MMemu::tlb_ac_a_o
protected

◆ tlb_ac_d_i

sc_signal<bool> MMemu::tlb_ac_d_i
protected

◆ tlb_ac_d_o

sc_signal<bool> MMemu::tlb_ac_d_o
protected

◆ tlb_ac_r_i

sc_signal<bool> MMemu::tlb_ac_r_i
protected

◆ tlb_ac_r_o

sc_signal<bool> MMemu::tlb_ac_r_o
protected

◆ tlb_ac_u_i

sc_signal<bool> MMemu::tlb_ac_u_i
protected

◆ tlb_ac_u_o

sc_signal<bool> MMemu::tlb_ac_u_o
protected

◆ tlb_ac_w_i

sc_signal<bool> MMemu::tlb_ac_w_i
protected

◆ tlb_ac_w_o

sc_signal<bool> MMemu::tlb_ac_w_o
protected

◆ tlb_ac_x_i

sc_signal<bool> MMemu::tlb_ac_x_i
protected

◆ tlb_ac_x_o

sc_signal<bool> MMemu::tlb_ac_x_o
protected

◆ tlb_adr_i

sc_signal<sc_uint<20> > MMemu::tlb_adr_i
protected

◆ tlb_flush

sc_in<bool> MMemu::tlb_flush

◆ tlb_hit

sc_signal<bool> MMemu::tlb_hit
protected

◆ tlb_miss

sc_signal<bool> MMemu::tlb_miss
protected

◆ tlb_pa_o

sc_signal<sc_uint<20> > MMemu::tlb_pa_o
protected

◆ tlb_req

sc_signal<bool> MMemu::tlb_req
protected

◆ tlb_superpage_i

sc_signal<bool> MMemu::tlb_superpage_i
protected

◆ tlb_superpage_o

sc_signal<bool> MMemu::tlb_superpage_o
protected

◆ tlb_va_o

sc_signal<sc_uint<20> > MMemu::tlb_va_o
protected

◆ tlb_wr

sc_signal<bool> MMemu::tlb_wr
protected

◆ way_wp

sc_signal<sc_uint<32> > MMemu::way_wp[CFG_MEMU_WPORTS]
protected

◆ wb_ack_i

sc_in<bool> MMemu::wb_ack_i

◆ wb_adr_o

sc_out<sc_uint<32> > MMemu::wb_adr_o

◆ wb_bte_o

sc_out<sc_uint<2> > MMemu::wb_bte_o

◆ wb_cti_o

sc_out<sc_uint<3> > MMemu::wb_cti_o

◆ wb_cyc_o

sc_out<bool> MMemu::wb_cyc_o

◆ wb_dat_i

sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MMemu::wb_dat_i

◆ wb_dat_o

sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MMemu::wb_dat_o

◆ wb_sel_o

sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > MMemu::wb_sel_o

◆ wb_stb_o

sc_out<bool> MMemu::wb_stb_o

◆ wb_we_o

sc_out<bool> MMemu::wb_we_o

◆ wiadr_busif

sc_signal<sc_uint<32> > MMemu::wiadr_busif
protected

◆ wiadr_rp

sc_signal<sc_uint<32> > MMemu::wiadr_rp[CFG_MEMU_RPORTS]
protected

◆ wp_ac_w

sc_out<bool> MMemu::wp_ac_w[CFG_MEMU_WPORTS]

◆ wp_ack

sc_out<bool> MMemu::wp_ack[CFG_MEMU_WPORTS]

◆ wp_adr

sc_in<sc_uint<32> > MMemu::wp_adr[CFG_MEMU_WPORTS]

◆ wp_bank_bsel

sc_signal<sc_uint<4> > MMemu::wp_bank_bsel[CFG_MEMU_WPORTS]
protected

◆ wp_bank_data_in

sc_signal<sc_uint<32> > MMemu::wp_bank_data_in[CFG_MEMU_WPORTS]
protected

◆ wp_bank_data_out

sc_signal<sc_uint<32> > MMemu::wp_bank_data_out[CFG_MEMU_WPORTS]
protected

◆ wp_bank_rd

sc_signal<bool> MMemu::wp_bank_rd[CFG_MEMU_WPORTS]
protected

◆ wp_bank_wr

sc_signal<bool> MMemu::wp_bank_wr[CFG_MEMU_WPORTS]
protected

◆ wp_bsel

sc_in<sc_uint<4> > MMemu::wp_bsel[CFG_MEMU_WPORTS]

◆ wp_busif_nolinelock

sc_signal<bool> MMemu::wp_busif_nolinelock[CFG_MEMU_WPORTS]
protected

◆ wp_busif_op

sc_signal<EBusIfOperation> MMemu::wp_busif_op[CFG_MEMU_WPORTS]
protected

◆ wp_cache_op

sc_in<sc_uint<3> > MMemu::wp_cache_op[CFG_MEMU_WPORTS]

◆ wp_data

sc_in<sc_uint<32> > MMemu::wp_data[CFG_MEMU_WPORTS]

◆ wp_direct

sc_in<bool> MMemu::wp_direct[CFG_MEMU_WPORTS]

◆ wp_lres_scond

sc_in<bool> MMemu::wp_lres_scond[CFG_MEMU_WPORTS]

◆ wp_paging

sc_in<bool> MMemu::wp_paging[CFG_MEMU_WPORTS]

◆ wp_scond_ok

sc_out<bool> MMemu::wp_scond_ok[CFG_MEMU_WPORTS]

◆ wp_tag_in

sc_signal<SCacheTag> MMemu::wp_tag_in[CFG_MEMU_WPORTS]
protected

◆ wp_tag_out

sc_signal<SCacheTag> MMemu::wp_tag_out[CFG_MEMU_WPORTS]
protected

◆ wp_tag_rd

sc_signal<bool> MMemu::wp_tag_rd[CFG_MEMU_WPORTS]
protected

◆ wp_tag_wr

sc_signal<bool> MMemu::wp_tag_wr[CFG_MEMU_WPORTS]
protected

◆ wp_trap_no_u

sc_in<bool> MMemu::wp_trap_no_u[CFG_MEMU_WPORTS]

◆ wp_trap_u

sc_in<bool> MMemu::wp_trap_u[CFG_MEMU_WPORTS]

◆ wp_wr

sc_in<bool> MMemu::wp_wr[CFG_MEMU_WPORTS]

◆ writePorts

MWritePort* MMemu::writePorts[CFG_MEMU_WPORTS]

The documentation for this class was generated from the following files: