ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
exu.h
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1 /*************************************************************************
2 
3  This file is part of the ParaNut project.
4 
5  Copyright (C) 2010-2022 Alexander Bahle <alexander.bahle@hs-augsburg.de>
6  Christian H. Meyer <christian.meyer@hs-augsburg.de>
7  Gundolf Kiefer <gundolf.kiefer@hs-augsburg.de>
8  Nico Borgsmüller <nico.borgsmueller@hs-augsburg.de>
9  Hochschule Augsburg, University of Applied Sciences
10 
11  Description:
12  This is a SystemC model of the execution unit (EXU) of the ParaNut.
13  The EXU contains the ALU, the register file, the capability to
14  decode instructions. It interfaces with the IFU and the LSU.
15 
16  Redistribution and use in source and binary forms, with or without modification,
17  are permitted provided that the following conditions are met:
18 
19  1. Redistributions of source code must retain the above copyright notice, this
20  list of conditions and the following disclaimer.
21 
22  2. Redistributions in binary form must reproduce the above copyright notice,
23  this list of conditions and the following disclaimer in the documentation and/or
24  other materials provided with the distribution.
25 
26  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
27  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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31  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
33  ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 
37  *************************************************************************/
38 
39 #pragma once
40 
41 #include "base.h"
42 #include "paranut-config.h"
43 #include "mextension.h"
44 #include "exu_csr.h"
45 
46 #include <systemc.h>
47 
48 #define REGISTERS 32
49 
50 // **************** RISC-V ISA Encoding *************
51 typedef enum { RType, IType, SType, BType, UType, JType } EAluRISCVType;
52 
53 typedef enum {
54  LOAD = 0x03,
55  PARA = 0x0B, // custom-0: ParaNut Extension
56  MISC_MEM = 0x0F,
57  OP_IMM = 0x13,
58  AUIPC = 0x17,
59  STORE = 0x23,
60  OP = 0x33,
61  LUI = 0x37,
62  BRANCH = 0x63,
63  JALR = 0x67,
64  JAL = 0x6F,
65  SYSTEM = 0x73,
66  AMO = 0x2F,
67 } EOpRISCV;
68 
69 typedef enum {
70  // group OP and OP_IMM:
71  afAdd = 0x0,
72  afSub = 0x0, // AF of afAdd
73  afSll = 0x1,
74  afSlt = 0x2,
75  afSltu = 0x3,
76  afXor = 0x4,
77  afSrl = 0x5,
78  afSra = 0x5, // AF of afSrl
79  afOr = 0x6,
80  afAnd = 0x7,
81  afEq = 0x8,
82  afBltu = 0x9,
83  afBlt = 0xA,
85 
86 // **************** EXU States *************
87 typedef enum {
97  // ParaNut extension states:
102  // Exception states:
106  // Special states (for extensions etc.)
107 #if CFG_EXU_M_EXTENSION == 1
110 #endif
111  // Debug states:
114 } EExuState;
115 
116 typedef enum {
129 
130  // Special Operation (for extensions etc.)
131 #if CFG_EXU_M_EXTENSION == 1
133 #endif
134 } EExuOp;
135 
136 
137 
138 // **************** MExu ************************
139 
140 class MExu : public ::sc_core::sc_module {
141 public:
142 
143  // Ports ...
144  sc_in<bool> clk, reset;
145 
146  // to IFU ...
148  sc_out<sc_uint<32> > ifu_jump_adr; // jump address
150  sc_in<sc_uint<32> > ifu_ir, ifu_pc, ifu_npc; // expected to be registered (fast) outputs
151  sc_in<bool> ifu_ac_x, ifu_ac_u;
152 
153  // to Load/Store Unit (LSU)...
154  sc_out<bool> lsu_rd, lsu_wr, lsu_flush;
155  sc_out<sc_uint<3> > lsu_cache_op;
156  sc_in<bool> lsu_ack;
157  sc_in<bool> lsu_align_err;
158  sc_out<sc_uint<2> > lsu_width; // "00" = word, "01" = byte, "10" = half word
159  sc_out<bool> lsu_exts;
160  sc_out<sc_uint<32> > lsu_adr;
161  sc_in<sc_uint<32> > lsu_rdata;
162  sc_out<sc_uint<32> > lsu_wdata;
163  sc_out<bool> lsu_lres_scond;
164  sc_in<bool> lsu_scond_ok;
165  sc_out<bool> lsu_trap_u, lsu_trap_no_u;
166  sc_in<bool> lsu_ac_r, lsu_ac_w, lsu_ac_u;
167  // TODO: omit checking the ac_u bit in the EXU. Instead, check trap_u and trap_no_u bits in MemU
168 
169 
170  // TBD:
171  // 1. Rename the following ports to properly relect their (usual) peer component.
172  // (see ports up to here)
173  // 2. Complete comments accordingly
174 
175  // to [[ TBD: specify the peer component ]]: Exception signals
176  sc_in<bool> xsel;
177  sc_in<bool> ex_i;
178  sc_out<bool> ex_o;
179  sc_in<sc_uint<5> > cause_i;
180  sc_out<sc_uint<5> > cause_o;
181 
182  // to other EXUs: Mode 1 syncronization signals
183  sc_in<bool> sync_i; // Sync daisy chain input: Connected to 'sync_o' of the next CoPU or constant '1' for the last CoPU
184  sc_out<bool> sync_o; // Sync daisy chain output: Drives 0 if this core is busy or 'sync_i' otherwise
185  sc_in<bool> sync_next; // Global signal from the CePU to indicate that the next instruction is to be executed
186  // (connected to CePU 'sync_o')
187 
188  // to [[ TBD: specify the peer component ]]: Mode 2 linked mode signals
189  sc_in<bool> m2_ir_valid;
190  sc_in<sc_uint<32> > m2_ir, m2_pc;
191  sc_in<bool> m2_ac_x, m2_ac_u;
192 
193  // to CePU [[ TBD: specify the peer component; "CePU" is ambiguous ]]
194  sc_in<bool> enable, linked;
195  sc_out<bool> haltreq;
196 
197  // to CoPUs [[ TBD: specify the peer component; "CePU" is ambiguous ]]
198  sc_out<sc_uint<CFG_NUT_CPU_CORES> > m3_pnce;
199  sc_out<sc_uint<CFG_NUT_CPU_CORES> > m3_pnlm;
200  sc_out<sc_uint<CFG_NUT_CPU_CORES> > m3_pnxsel;
201  sc_in<sc_uint<CFG_NUT_CPU_CORES> > m3_pnhaltreq, m3_pnx;
202  sc_in<sc_uint<2> > m3_priv_mode_i;
203  sc_out<sc_uint<2> > m3_priv_mode_o;
204 
205  // to interrupt controller ...
206  sc_in<bool> m3_ir_request;
207  sc_in<sc_uint<5> > m3_ir_id;
208  sc_out<bool> m3_ir_ack;
209  sc_out<bool> m3_ir_enable;
210 
211  // special outputs ...
213  // cache enable control signals (CePU only)
214 
215  // to Debug Unit ...
216  sc_in<bool> dbg_req;
217 
218  // to CSR Module
220  sc_out<bool> csr_cpu_enabled;
221  sc_out<sc_uint<5> > csr_ex_id_reg;
222  sc_out<bool> csr_sret_dreg;
223  sc_out<bool> csr_exu_exception;
224  sc_out<bool> csr_irq_dreg;
226  sc_out<sc_uint<5> > csr_csr_rs1_reg;
227  sc_out<sc_uint<32> > csr_csr_op_a;
228  sc_out<sc_uint<3> > csr_csr_function_reg;
229  sc_out<sc_uint<12> > csr_csr_adr_reg;
230  sc_out<sc_uint<32> > csr_csr_tval;
231 
232  sc_out<sc_uint<32> > csr_pc, csr_ir;
233 
234  sc_out<sc_uint<CFG_NUT_CPU_CORES_LD> > csr_hartID;
235  sc_out<bool> csr_inCePU;
236  sc_out<bool> csr_linked;
237  sc_out<bool> csr_enable;
238  sc_out<sc_uint<5> > csr_cause;
239  sc_out<sc_uint<CFG_NUT_CPU_CORES> > csr_m3_pnhaltreq, csr_m3_pnx;
240  sc_out<sc_uint<2> > csr_m3_priv_mode;
241 
242 #if CFG_EXU_PERFCOUNT_ENABLE == 1
243  // Perfcount signals ...
244  sc_out<bool> csr_perf_inc;
245  sc_out<sc_uint<CFG_EXU_PERFCOUNTERS_LD> > csr_perf_addr;
246 #endif
247 
248  // to/from CSR Module
249  sc_in<bool> csr_exception; // Writes to read-only CSRs raise an exeption
250  sc_in<sc_uint<32> > csr_rdata;
251  sc_in<bool> csr_delegate_dreg; // jump to stvec when set on exception
252  sc_in<bool> csr_isHalted;
253  sc_in<bool> csr_cache_flush; // CSR module requests cache flushing
254  sc_out<bool> csr_ack;
256 
257  sc_in<bool> csr_mstatus_SIE, // jump to stvec when set on exception
264  sc_in<sc_uint<32> >
273 
274  sc_in<sc_uint<CFG_NUT_CPU_CORES> >
278 
280 
282  sc_in<sc_uint<20> > csr_satp_root_ppn;
283 
284  // to MMU
285  sc_out<bool> tlb_flush;
286 
288  sc_out<sc_uint<20> > root_ppn;
289 
290  // Misc. ports ...
291  // TBD: Are they still necessary? -> Eliminate or document
292  // (HLS reasons, should be optimized out while synthetization)
293  // these could be generics in VHDL, but current tools don't support that
294  sc_in<sc_uint<CFG_NUT_CPU_CORES_LD> > hartID;
295  // 'inCePU' indicates whether the surrounding CPU is the CePU.
296  // 'mode2Cap' indicates the maximum mode supported.
297  // The (only) possible combinations of ('inCePU', 'mode2Cap') are:
298  // (true, true) // CePU, all capabilities
299  // (false, true) // CoPU supporting modes 0-2
300  // (false, false) // CoPU supporting modes 0-1 (no unlinked mode)
301  sc_in<bool> inCePU, mode2Cap;
302 
303 
304 
305  // Constructor...
306  SC_HAS_PROCESS (MExu);
307  MExu (sc_module_name name)
308  : sc_module (name)
309 #if CFG_EXU_M_EXTENSION == 1
310  // Instantiate M-Extension submodule
311  , mext ("MExtension")
312 #endif
313  {
314  // EXU methods
316  SC_METHOD (MainCombMethod);
317  sensitive << reset << enable << alu_result << ir_valid << lsu_ack << lsu_width_dreg << lsu_align_err
329  << ex_CoPU_dreg << csr_dcsr_step << xsel << csr_dpc << pc << dbg_reg;
330 #if CFG_EXU_M_EXTENSION == 1
331  // Add M-Extension signals to MainCombMethods sensitivity list
333 
334  // Route M-Extension submodule signals
335  mext.clk (clk);
336  mext.reset (reset);
341  mext.op_a (op_a_dreg);
342  mext.op_b (op_b_dreg);
346 #endif
347 
349  SC_METHOD (Mode2Method);
350  sensitive << linked << ifu_ir << ifu_ir_valid << ifu_pc << m2_ir_valid << m2_ir << m2_pc
351  << ifu_ac_x << ifu_ac_u << m2_ac_x << m2_ac_u << inCePU << mode2Cap;
352 
353  // Alu methods
354  SC_METHOD (AluShiftMethod);
355  sensitive << alu_s_enable << alu_s_function << alu_s_amount << op_a_dreg;
356  SC_METHOD (AluCombMethod);
359 
360  SC_METHOD (CSRMethod);
361  sensitive << pop_priv_ir_stack_dreg << csr_instr << exception << irq_dreg << dbg
366  << dbg_enter_dreg;
367 #if CFG_EXU_PERFCOUNT_ENABLE == 1
368  sensitive << perf_inc << perf_addr;
369 #endif
370  }
371 
372  // Functions...
373  void Trace (sc_trace_file * tf, int levels = 1);
374 
375 #ifndef __SYNTHESIS__
376  void DisplayStatistics () { return perf_mon_.Display (this->name ()); }
377  bool IsHalted () { return csr_isHalted.read (); }
378 #endif
379 
380  // Processes...
381  void AluCombMethod ();
382  void AluShiftMethod ();
383 
384  void MainMethod ();
385  void MainCombMethod ();
386  void DecodeMethod ();
387 
388  void Mode2Method ();
389  void CSRMethod ();
390 
391 protected:
392  // Debug state ...
393  sc_signal<bool> dbg, dbg_reg;
394 
395  // Exception handling ...
396  sc_signal<sc_uint<5> > ex_id, ex_id_reg;
397  sc_signal<bool> ex_handle_reg, ex_handle; // ex_handle_reg is 1 during exception handling (gets reset by executing mret instruction)
398  sc_signal<bool> exception; // internal signal, active for one cycle (ExuExOrIrq state) to
399  // trigger saving of the exception state CSRs (mepc, mcause, ...)
400  sc_signal<bool> ignore_ir_reg, ignore_ir;
401  sc_signal<bool> m3_ir_request_reg; // save ir_request so we can prioritize CoPU excecptions
402 
403  // CPU general purpose integer registers ...
404  sc_signal<sc_uint<32> > gp_regs[REGISTERS];
405  sc_signal<sc_uint<32> > gpr_in; // Input value for GPR writes
406  sc_signal<bool> gpr_write; // Write gpr_in value to GPR specified by gpr_sel_dreg
407 
408  // Exu signals/registers ...
409  sc_signal<sc_uint<EX_ID_LENGTH> > state_reg, state;
410  sc_signal<bool> stall_decode;
411  sc_signal<bool> internal_next;
412 
413  // Exu Mode 1 signals/registers ...
414  sc_signal<bool> sync_reg, sync;
415  sc_signal<bool> ir_valid;
416  sc_signal<sc_uint<32> > ir, pc;
417  sc_signal<bool> ac_x, ac_u;
418 
419  // Helper methods...
420  void InstructionTrace ();
421  void DumpRegisterInfo ();
422  void DumpRegisterChange ();
423 
424  // CSR method signals/registers ...
425  sc_signal<sc_uint<3> > csr_function_reg;
426  sc_signal<sc_uint<12> > csr_adr_reg;
427  sc_signal<sc_uint<5> > csr_rs1_reg;
428  sc_signal<bool> csr_instr;
429  sc_signal<sc_uint<32> > csr_op_a;
430  sc_signal<sc_uint<32> > csr_tval;
431 
432  // ALU signals ...
433  sc_signal<bool> alu_finished, alu_branch;
434  sc_signal<sc_uint<32> > alu_result;
435 
436  sc_signal<sc_uint<32> > alu_result_reg; // Register for saving alu return value
437  sc_signal<bool> alu_branch_reg; // Register for saving alu branch decision value
438 
439  sc_signal<sc_uint<2> > alu_s_function;
440  sc_signal<sc_uint<5> > alu_s_amount;
441  sc_signal<bool> alu_s_ready, alu_s_enable;
442  sc_signal<sc_uint<32> > alu_s_result;
443 
444 #if CFG_EXU_M_EXTENSION == 1
445  // M-Extension module ...
447  // M-Extension signals/registers ...
448  sc_signal<bool> alu_m_enable, alu_m_valid;
449  sc_signal<sc_uint<32> > alu_m_result;
450  sc_signal<bool> alu_d_enable, alu_d_valid;
451  sc_signal<sc_uint<32> > alu_d_result;
452  sc_signal<bool> alu_md_dreg; // Decode Register: 1 for div operations, 0 for mul operations
453  sc_signal<sc_uint<2> > alu_md_function_dreg; // Decode Register: See EMExtFunc enum for value description
454 #endif
455 
456 #if CFG_EXU_PERFCOUNT_ENABLE == 1
457  // Perfcount signals ...
458  sc_signal<bool> perf_inc;
459  sc_signal<sc_uint<CFG_EXU_PERFCOUNTERS_LD> > perf_addr;
460 #endif
461 
462  // Decode registers ...
463  sc_signal<sc_uint<32> >
464  op_a_dreg, // Operand A for ALU/... operations (depends on instruction format)
465  op_b_dreg, // Operand B for ALU/... operations (depends on instruction format)
466  branch_a_dreg, // Operand A for Branch decision (B-Type instruction format: PC)
467  branch_b_dreg; // Operand B for Branch decision (B-Type instruction format: sign extended 12 bit immediat)
468  sc_signal<sc_uint<5> > gpr_sel_dreg; // Destination register select
469  sc_signal<bool>
470  sret_dreg, // Set to trigger usage of mepc - sepc otherwise
471  xret_dreg, // Used when executing xret insructions
472  pop_priv_ir_stack_dreg, // trigger popping the Privilege and Global Interrupt-Enable Stack
473  alu_af_dreg, // Set to use alternate function (Add->Sub, Srl->Sra, see EAluFuncRISCV)
474  alu_branch_dreg, // Set to calculate branch result
475  illegal_insn_dreg, // Set if illegal instruction was decoded
476  insn_page_fault_dreg, // Set on unprivileged instruction accesses
477  ex_CoPU_dreg, // Set if ex_i was set during instruction decode (handle CoPU exceptions)
478  irq_dreg, // Set if m3_ir_request is set during instruction decode (handle interrupt request)
479  step_dreg, // Set when csr_dcsr_step is set, enter debug mode automatically after one instruction
480  ecall_dreg, // Set to trigger ecall exception
481  ebreak_dreg, // Set to trigger ebreak exception
482  flush_dreg, // Set for fence and PN_CFLUSH, PN_CINVALIDATE, PN_CWRITEBACK instructions (flush IFU and LSU write buffer)
483  lsu_rd_dreg, // 1 for load/lres operations, 0 for store/scond operations
484  lres_scond_dreg, // Set for lres and scond operations
485  dbg_enter_dreg; // Set while entering debug mode
486  sc_signal<sc_uint<2> > lsu_width_dreg; // set to indicate L/S width or cache operation
487  sc_signal<sc_uint<3> > cache_op_dreg; // Set for the cache operations (flush, invalidate, writeback,...)
488  sc_signal<sc_uint<4> >
489  exu_op_dreg, // EXU Execute (Stage) operation (see EExuOp)
490  alu_function_dreg; // ALU operation (see EAluFuncRISCV)
491 
492 
493  // Performance Monitor ...
495 };
Helpers, Makros and performance measuring Classes used in most ParaNut files.
CPU performance monitor class.
Definition: base.h:567
void Display(const char *name=NULL)
Display the collected performance information.
Definition: base.cpp:299
Definition: exu.h:140
sc_signal< bool > xret_dreg
Definition: exu.h:471
sc_signal< sc_uint< 5 > > ex_id
Definition: exu.h:396
sc_out< sc_uint< CFG_NUT_CPU_CORES > > m3_pnxsel
Definition: exu.h:200
CPerfMonCPU perf_mon_
Definition: exu.h:494
sc_signal< bool > lsu_rd_dreg
Definition: exu.h:483
sc_signal< sc_uint< 32 > > alu_result
Definition: exu.h:434
sc_in< bool > csr_mstatus_SUM
Definition: exu.h:258
sc_signal< bool > stall_decode
Definition: exu.h:410
sc_out< bool > haltreq
Definition: exu.h:195
sc_signal< sc_uint< 2 > > alu_md_function_dreg
Definition: exu.h:453
sc_signal< sc_uint< 32 > > ir
Definition: exu.h:416
sc_signal< bool > ignore_ir
Definition: exu.h:400
sc_in< bool > csr_exception
Definition: exu.h:249
sc_in< bool > sync_i
Definition: exu.h:183
sc_in< sc_uint< 32 > > csr_mcause
Definition: exu.h:268
void InstructionTrace()
Definition: exu.cpp:262
sc_out< bool > sync_o
Definition: exu.h:184
sc_out< sc_uint< 32 > > lsu_adr
Definition: exu.h:160
bool IsHalted()
Definition: exu.h:377
sc_signal< sc_uint< CFG_EXU_PERFCOUNTERS_LD > > perf_addr
Definition: exu.h:459
sc_out< bool > m3_ir_ack
Definition: exu.h:208
sc_out< bool > csr_sret_dreg
Definition: exu.h:222
sc_signal< sc_uint< 32 > > branch_b_dreg
Definition: exu.h:467
sc_out< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnhaltreq
Definition: exu.h:239
sc_in< bool > enable
Definition: exu.h:194
sc_signal< bool > csr_instr
Definition: exu.h:428
sc_signal< sc_uint< 2 > > lsu_width_dreg
Definition: exu.h:486
sc_signal< bool > alu_branch_reg
Definition: exu.h:437
sc_signal< bool > alu_branch
Definition: exu.h:433
sc_out< bool > ifu_next
Definition: exu.h:147
sc_out< sc_uint< 3 > > lsu_cache_op
Definition: exu.h:155
sc_in< bool > lsu_ac_u
Definition: exu.h:166
sc_signal< bool > internal_next
Definition: exu.h:411
sc_in< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnlm
Definition: exu.h:276
sc_out< bool > csr_cpu_enabled
Definition: exu.h:220
sc_signal< sc_uint< 32 > > op_b_dreg
Definition: exu.h:465
void DisplayStatistics()
Definition: exu.h:376
sc_in< bool > csr_mstatus_TVM
Definition: exu.h:261
sc_in< bool > csr_ifu_paging_mode
Definition: exu.h:281
sc_in< bool > csr_delegate_dreg
Definition: exu.h:251
sc_signal< bool > alu_d_valid
Definition: exu.h:450
sc_in< bool > mode2Cap
Definition: exu.h:301
void AluCombMethod()
Definition: exu.cpp:349
sc_signal< bool > ignore_ir_reg
Definition: exu.h:400
sc_signal< bool > perf_inc
Definition: exu.h:458
sc_out< sc_uint< 5 > > csr_csr_rs1_reg
Definition: exu.h:226
sc_out< bool > lsu_paging_mode
Definition: exu.h:287
void DecodeMethod()
Definition: exu.cpp:477
sc_in< sc_uint< 32 > > m2_pc
Definition: exu.h:190
sc_in< bool > csr_cache_flush
Definition: exu.h:253
sc_in< bool > ifu_npc_valid
Definition: exu.h:149
sc_out< sc_uint< 3 > > csr_csr_function_reg
Definition: exu.h:228
void Trace(sc_trace_file *tf, int levels=1)
Definition: exu.cpp:66
sc_signal< bool > alu_s_enable
Definition: exu.h:441
sc_signal< bool > exception
Definition: exu.h:398
sc_signal< bool > ebreak_dreg
Definition: exu.h:481
sc_signal< sc_uint< 4 > > exu_op_dreg
Definition: exu.h:489
sc_in< bool > m2_ac_x
Definition: exu.h:191
sc_in< bool > csr_mstatus_SIE
Definition: exu.h:257
sc_out< sc_uint< 32 > > csr_pc
Definition: exu.h:232
sc_out< bool > csr_pop_priv_ir_stack_dreg
Definition: exu.h:225
sc_out< bool > lsu_wr
Definition: exu.h:154
sc_in< bool > csr_dcsr_ebreakm
Definition: exu.h:262
sc_in< sc_uint< 32 > > ifu_npc
Definition: exu.h:150
sc_signal< sc_uint< 3 > > cache_op_dreg
Definition: exu.h:487
sc_in< bool > lsu_align_err
Definition: exu.h:157
sc_in< sc_uint< CFG_NUT_CPU_CORES_LD > > hartID
Definition: exu.h:294
sc_in< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnxsel
Definition: exu.h:277
sc_in< bool > inCePU
Definition: exu.h:301
sc_out< sc_uint< CFG_EXU_PERFCOUNTERS_LD > > csr_perf_addr
Definition: exu.h:245
sc_in< sc_uint< 32 > > csr_dpc
Definition: exu.h:270
sc_signal< sc_uint< 5 > > ex_id_reg
Definition: exu.h:396
sc_signal< sc_uint< EX_ID_LENGTH > > state_reg
Definition: exu.h:409
sc_in< sc_uint< 32 > > csr_stvec
Definition: exu.h:267
sc_in< bool > lsu_ac_r
Definition: exu.h:166
sc_out< bool > lsu_exts
Definition: exu.h:159
sc_in< sc_uint< 32 > > lsu_rdata
Definition: exu.h:161
sc_in< bool > m2_ac_u
Definition: exu.h:191
sc_in< bool > m2_ir_valid
Definition: exu.h:189
sc_out< bool > lsu_trap_no_u
Definition: exu.h:165
sc_in< sc_uint< 32 > > csr_mideleg
Definition: exu.h:265
sc_in< bool > ex_i
Definition: exu.h:177
sc_out< bool > lsu_lres_scond
Definition: exu.h:163
sc_out< bool > m3_dcache_enable
Definition: exu.h:212
sc_out< bool > csr_dbg
Definition: exu.h:219
void MainCombMethod()
Definition: exu.cpp:842
sc_signal< sc_uint< 32 > > csr_op_a
Definition: exu.h:429
sc_out< sc_uint< 20 > > root_ppn
Definition: exu.h:288
sc_signal< bool > insn_page_fault_dreg
Definition: exu.h:476
sc_signal< bool > ex_handle_reg
Definition: exu.h:397
void DumpRegisterChange()
Definition: exu.cpp:254
sc_in< sc_uint< 32 > > csr_mepc
Definition: exu.h:271
sc_signal< bool > ac_x
Definition: exu.h:417
sc_out< sc_uint< CFG_NUT_CPU_CORES > > m3_pnce
Definition: exu.h:198
sc_out< bool > tlb_flush
Definition: exu.h:285
sc_signal< bool > lres_scond_dreg
Definition: exu.h:484
sc_out< sc_uint< 5 > > cause_o
Definition: exu.h:180
sc_signal< bool > alu_af_dreg
Definition: exu.h:473
sc_in< sc_uint< 32 > > ifu_pc
Definition: exu.h:150
sc_signal< bool > alu_finished
Definition: exu.h:433
sc_in< bool > clk
Definition: exu.h:144
sc_signal< bool > pop_priv_ir_stack_dreg
Definition: exu.h:472
sc_in< bool > ifu_ac_x
Definition: exu.h:151
sc_signal< sc_uint< EX_ID_LENGTH > > state
Definition: exu.h:409
sc_signal< sc_uint< 32 > > op_a_dreg
Definition: exu.h:464
void CSRMethod()
Definition: exu.cpp:1431
sc_out< bool > csr_linked
Definition: exu.h:236
sc_in< bool > ifu_ac_u
Definition: exu.h:151
sc_out< sc_uint< CFG_NUT_CPU_CORES_LD > > csr_hartID
Definition: exu.h:234
sc_out< bool > csr_dbg_reg
Definition: exu.h:219
sc_signal< bool > m3_ir_request_reg
Definition: exu.h:401
sc_out< bool > ifu_reset
Definition: exu.h:147
sc_signal< bool > ex_handle
Definition: exu.h:397
sc_out< sc_uint< 32 > > lsu_wdata
Definition: exu.h:162
sc_out< sc_uint< 12 > > csr_csr_adr_reg
Definition: exu.h:229
sc_signal< sc_uint< 32 > > alu_m_result
Definition: exu.h:449
sc_in< bool > lsu_scond_ok
Definition: exu.h:164
sc_out< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnx
Definition: exu.h:239
sc_out< bool > ifu_paging_mode
Definition: exu.h:287
sc_in< bool > sync_next
Definition: exu.h:185
sc_out< sc_uint< 5 > > csr_cause
Definition: exu.h:238
sc_in< bool > csr_m3_dcache_enable
Definition: exu.h:279
sc_out< bool > csr_dbg_enter_dreg
Definition: exu.h:219
sc_out< sc_uint< 32 > > csr_ir
Definition: exu.h:232
sc_signal< bool > sync
Definition: exu.h:414
sc_in< bool > m3_ir_request
Definition: exu.h:206
sc_signal< bool > irq_dreg
Definition: exu.h:478
sc_signal< bool > alu_s_ready
Definition: exu.h:441
sc_out< bool > lsu_trap_u
Definition: exu.h:165
sc_signal< sc_uint< 2 > > alu_s_function
Definition: exu.h:439
MExu(sc_module_name name)
Definition: exu.h:307
sc_signal< sc_uint< 12 > > csr_adr_reg
Definition: exu.h:426
sc_in< bool > lsu_ac_w
Definition: exu.h:166
sc_signal< bool > alu_m_valid
Definition: exu.h:448
sc_out< bool > csr_ack
Definition: exu.h:254
sc_in< bool > linked
Definition: exu.h:194
sc_out< bool > ifu_flush
Definition: exu.h:147
sc_in< bool > csr_isHalted
Definition: exu.h:252
sc_in< sc_uint< CFG_NUT_CPU_CORES > > m3_pnhaltreq
Definition: exu.h:201
sc_out< bool > csr_exu_exception
Definition: exu.h:223
sc_in< bool > xsel
Definition: exu.h:176
sc_in< sc_uint< 32 > > csr_mtvec
Definition: exu.h:269
sc_signal< sc_uint< 5 > > csr_rs1_reg
Definition: exu.h:427
sc_in< bool > csr_m3_icache_enable
Definition: exu.h:279
sc_signal< bool > alu_md_dreg
Definition: exu.h:452
sc_in< bool > csr_dcsr_step
Definition: exu.h:263
sc_signal< bool > flush_dreg
Definition: exu.h:482
sc_out< sc_uint< 2 > > m3_priv_mode_o
Definition: exu.h:203
sc_out< sc_uint< CFG_NUT_CPU_CORES > > m3_pnlm
Definition: exu.h:199
sc_signal< bool > illegal_insn_dreg
Definition: exu.h:475
sc_out< sc_uint< 32 > > ifu_jump_adr
Definition: exu.h:148
sc_in< bool > csr_lsu_paging_mode
Definition: exu.h:281
sc_in< bool > reset
Definition: exu.h:144
void DumpRegisterInfo()
Definition: exu.cpp:232
sc_in< sc_uint< 32 > > csr_rdata
Definition: exu.h:250
sc_in< sc_uint< 32 > > csr_mip
Definition: exu.h:272
sc_signal< bool > sync_reg
Definition: exu.h:414
sc_signal< bool > alu_d_enable
Definition: exu.h:450
sc_out< bool > csr_enable
Definition: exu.h:237
sc_in< bool > csr_mstatus_MIE
Definition: exu.h:259
sc_in< sc_uint< 32 > > ifu_ir
Definition: exu.h:150
sc_signal< sc_uint< 5 > > gpr_sel_dreg
Definition: exu.h:468
sc_signal< bool > dbg_enter_dreg
Definition: exu.h:485
sc_signal< sc_uint< 32 > > csr_tval
Definition: exu.h:430
sc_out< bool > csr_perf_inc
Definition: exu.h:244
sc_signal< bool > ir_valid
Definition: exu.h:415
sc_signal< sc_uint< 32 > > branch_a_dreg
Definition: exu.h:466
sc_in< sc_uint< 32 > > m2_ir
Definition: exu.h:190
sc_out< sc_uint< 5 > > csr_ex_id_reg
Definition: exu.h:221
sc_signal< sc_uint< 3 > > csr_function_reg
Definition: exu.h:425
sc_signal< sc_uint< 32 > > gp_regs[REGISTERS]
Definition: exu.h:404
sc_in< sc_uint< 5 > > cause_i
Definition: exu.h:179
sc_signal< bool > dbg_reg
Definition: exu.h:393
sc_signal< sc_uint< 32 > > gpr_in
Definition: exu.h:405
sc_out< bool > lsu_rd
Definition: exu.h:154
sc_signal< bool > alu_branch_dreg
Definition: exu.h:474
sc_in< sc_uint< 32 > > csr_sepc
Definition: exu.h:266
void Mode2Method()
Definition: exu.cpp:1413
sc_out< bool > m3_ir_enable
Definition: exu.h:209
sc_out< sc_uint< 32 > > csr_csr_tval
Definition: exu.h:230
sc_out< sc_uint< 2 > > lsu_width
Definition: exu.h:158
sc_signal< bool > dbg
Definition: exu.h:393
sc_signal< sc_uint< 32 > > alu_s_result
Definition: exu.h:442
sc_out< bool > ifu_jump
Definition: exu.h:147
sc_in< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnce
Definition: exu.h:275
sc_in< bool > ifu_ir_valid
Definition: exu.h:149
sc_out< bool > csr_inCePU
Definition: exu.h:235
sc_in< bool > csr_mstatus_TSR
Definition: exu.h:260
sc_signal< sc_uint< 32 > > alu_result_reg
Definition: exu.h:436
sc_in< sc_uint< 2 > > m3_priv_mode_i
Definition: exu.h:202
sc_signal< sc_uint< 5 > > alu_s_amount
Definition: exu.h:440
sc_out< bool > csr_irq_dreg
Definition: exu.h:224
sc_out< sc_uint< 2 > > csr_m3_priv_mode
Definition: exu.h:240
sc_signal< bool > gpr_write
Definition: exu.h:406
sc_in< sc_uint< 2 > > csr_priv_mode
Definition: exu.h:255
sc_signal< bool > alu_m_enable
Definition: exu.h:448
sc_out< bool > lsu_flush
Definition: exu.h:154
sc_in< sc_uint< CFG_NUT_CPU_CORES > > m3_pnx
Definition: exu.h:201
sc_signal< bool > sret_dreg
Definition: exu.h:470
sc_signal< sc_uint< 32 > > pc
Definition: exu.h:416
sc_signal< sc_uint< 4 > > alu_function_dreg
Definition: exu.h:490
MMExtension mext
Definition: exu.h:446
void AluShiftMethod()
Definition: exu.cpp:277
sc_in< sc_uint< 5 > > m3_ir_id
Definition: exu.h:207
sc_signal< sc_uint< 32 > > alu_d_result
Definition: exu.h:451
void MainMethod()
Definition: exu.cpp:429
sc_signal< bool > ex_CoPU_dreg
Definition: exu.h:477
sc_out< bool > m3_icache_enable
Definition: exu.h:212
sc_signal< bool > ac_u
Definition: exu.h:417
sc_signal< bool > step_dreg
Definition: exu.h:479
sc_in< sc_uint< 2 > > csr_load_store_priv_mode
Definition: exu.h:255
sc_out< sc_uint< 32 > > csr_csr_op_a
Definition: exu.h:227
sc_in< bool > dbg_req
Definition: exu.h:216
sc_in< bool > lsu_ack
Definition: exu.h:156
sc_out< bool > ex_o
Definition: exu.h:178
sc_in< sc_uint< 20 > > csr_satp_root_ppn
Definition: exu.h:282
sc_signal< bool > ecall_dreg
Definition: exu.h:480
Definition: mextension.h:61
sc_in< sc_uint< 2 > > md_func
Definition: mextension.h:67
sc_out< sc_uint< 32 > > d_result
Definition: mextension.h:71
sc_out< bool > d_valid
Definition: mextension.h:70
sc_out< bool > m_valid
Definition: mextension.h:70
sc_out< sc_uint< 32 > > m_result
Definition: mextension.h:71
sc_in< bool > reset
Definition: mextension.h:64
sc_in< sc_uint< 32 > > op_a
Definition: mextension.h:68
sc_in< bool > m_enable
Definition: mextension.h:66
sc_in< bool > d_enable
Definition: mextension.h:66
sc_in< sc_uint< 32 > > op_b
Definition: mextension.h:68
sc_in< bool > clk
Definition: mextension.h:64
EAluFuncRISCV
Definition: exu.h:69
@ afSrl
Definition: exu.h:77
@ afSltu
Definition: exu.h:75
@ afAdd
Definition: exu.h:71
@ afOr
Definition: exu.h:79
@ afSra
Definition: exu.h:78
@ afXor
Definition: exu.h:76
@ afEq
Definition: exu.h:81
@ afBltu
Definition: exu.h:82
@ afBlt
Definition: exu.h:83
@ afSll
Definition: exu.h:73
@ afAnd
Definition: exu.h:80
@ afSub
Definition: exu.h:72
@ afSlt
Definition: exu.h:74
EExuState
Definition: exu.h:87
@ ExuXRETFinish
Definition: exu.h:96
@ ExuBranch
Definition: exu.h:92
@ ExuDiv
Definition: exu.h:108
@ ExuHalt
Definition: exu.h:98
@ ExuExJumpTvec
Definition: exu.h:105
@ ExuExWaitForCoPUs
Definition: exu.h:104
@ ExuXRET
Definition: exu.h:94
@ ExuMemWB
Definition: exu.h:90
@ ExuXRETCsrWait
Definition: exu.h:95
@ ExuMulDivWB
Definition: exu.h:109
@ ExuCACHECONT2
Definition: exu.h:101
@ ExuExecuteInsn
Definition: exu.h:88
@ ExuDBGEnter
Definition: exu.h:112
@ ExuCACHECONT
Definition: exu.h:100
@ ExuExOrIrq
Definition: exu.h:103
@ ExuJump
Definition: exu.h:91
@ ExuDBG
Definition: exu.h:113
@ ExuLSUFlush
Definition: exu.h:99
@ ExuCSR
Definition: exu.h:93
@ ExuMem
Definition: exu.h:89
EAluRISCVType
Definition: exu.h:51
@ IType
Definition: exu.h:51
@ RType
Definition: exu.h:51
@ UType
Definition: exu.h:51
@ SType
Definition: exu.h:51
@ JType
Definition: exu.h:51
@ BType
Definition: exu.h:51
#define REGISTERS
Definition: exu.h:48
EExuOp
Definition: exu.h:116
@ OpBranch
Definition: exu.h:120
@ OpMem
Definition: exu.h:121
@ OpException
Definition: exu.h:126
@ OpXRet
Definition: exu.h:123
@ OpCSR
Definition: exu.h:122
@ OpMulDiv
Definition: exu.h:132
@ OpParaNut
Definition: exu.h:125
@ OpHalt
Definition: exu.h:124
@ OpJump
Definition: exu.h:119
@ OpAlu
Definition: exu.h:118
@ OpDebug
Definition: exu.h:127
@ OpSFenceVMA
Definition: exu.h:128
@ OpNOP
Definition: exu.h:117
EOpRISCV
Definition: exu.h:53
@ OP_IMM
Definition: exu.h:57
@ JAL
Definition: exu.h:64
@ SYSTEM
Definition: exu.h:65
@ OP
Definition: exu.h:60
@ LUI
Definition: exu.h:61
@ AMO
Definition: exu.h:66
@ LOAD
Definition: exu.h:54
@ JALR
Definition: exu.h:63
@ PARA
Definition: exu.h:55
@ MISC_MEM
Definition: exu.h:56
@ BRANCH
Definition: exu.h:62
@ AUIPC
Definition: exu.h:58
@ STORE
Definition: exu.h:59
#define CFG_EXU_M_EXTENSION
RISC-V M-Extension.
Definition: paranut-config.h:141
#define PN_CLOCK_TRIGGERED(method_name)
Definition: base.h:595
Configuration Makros used in most ParaNut files.
sc_trace_file * tf
Definition: tlb_tb.cpp:94