ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
Public Member Functions | Public Attributes | Protected Attributes | List of all members
MTagRam Class Reference

#include <memu.h>

Inheritance diagram for MTagRam:
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Collaboration diagram for MTagRam:
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Public Member Functions

 MTagRam (sc_module_name name)
 
void Trace (sc_trace_file *tf, int level=1)
 
void MainThread ()
 

Public Attributes

sc_in< bool > clk
 
sc_in< bool > reset
 
sc_out< bool > ready
 
sc_in< bool > rd [TR_PORTS]
 
sc_in< bool > wr [TR_PORTS]
 
sc_in< bool > rd_way
 
sc_in< sc_uint< 32 > > adr [TR_PORTS]
 
sc_in< sc_uint< 32 > > wadr [TR_PORTS]
 
sc_in< SCacheTagtag_in [TR_PORTS]
 
sc_out< SCacheTagtag_out [TR_PORTS]
 

Protected Attributes

STagEntry ram_ [CFG_MEMU_CACHE_SETS]
 
sc_signal< bool > write_tag
 
sc_signal< sc_uint< CFG_MEMU_CACHE_WAYS_LD > > wtag_way
 
sc_signal< sc_uint< 32 > > wtag_iadr
 
sc_signal< sc_uint< 32 > > wtag_port
 
sc_signal< sc_uint< 6 > > use_reg [TR_PORTS+1]
 
sc_signal< sc_uint< 6 > > use_iadr_reg [TR_PORTS+1]
 
sc_signal< bool > use_wr_reg [TR_PORTS+1]
 
sc_signal< sc_uint< 8 > > counter
 

Constructor & Destructor Documentation

◆ MTagRam()

MTagRam::MTagRam ( sc_module_name  name)
inline

Member Function Documentation

◆ MainThread()

void MTagRam::MainThread ( )

◆ Trace()

void MTagRam::Trace ( sc_trace_file *  tf,
int  level = 1 
)

Member Data Documentation

◆ adr

sc_in<sc_uint<32> > MTagRam::adr[TR_PORTS]

◆ clk

sc_in<bool> MTagRam::clk

◆ counter

sc_signal<sc_uint<8> > MTagRam::counter
protected

◆ ram_

STagEntry MTagRam::ram_[CFG_MEMU_CACHE_SETS]
protected

◆ rd

sc_in<bool> MTagRam::rd[TR_PORTS]

◆ rd_way

sc_in<bool> MTagRam::rd_way

◆ ready

sc_out<bool> MTagRam::ready

◆ reset

sc_in<bool> MTagRam::reset

◆ tag_in

sc_in<SCacheTag> MTagRam::tag_in[TR_PORTS]

◆ tag_out

sc_out<SCacheTag> MTagRam::tag_out[TR_PORTS]

◆ use_iadr_reg

sc_signal<sc_uint<6> > MTagRam::use_iadr_reg[TR_PORTS+1]
protected

◆ use_reg

sc_signal<sc_uint<6> > MTagRam::use_reg[TR_PORTS+1]
protected

◆ use_wr_reg

sc_signal<bool> MTagRam::use_wr_reg[TR_PORTS+1]
protected

◆ wadr

sc_in<sc_uint<32> > MTagRam::wadr[TR_PORTS]

◆ wr

sc_in<bool> MTagRam::wr[TR_PORTS]

◆ write_tag

sc_signal<bool> MTagRam::write_tag
protected

◆ wtag_iadr

sc_signal<sc_uint<32> > MTagRam::wtag_iadr
protected

◆ wtag_port

sc_signal<sc_uint<32> > MTagRam::wtag_port
protected

◆ wtag_way

sc_signal<sc_uint<CFG_MEMU_CACHE_WAYS_LD> > MTagRam::wtag_way
protected

The documentation for this class was generated from the following files: