ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
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#include <memu.h>
Public Member Functions | |
MBankRam (sc_module_name name) | |
void | Trace (sc_trace_file *tf, int level=1) |
void | MainThread () |
Public Attributes | |
sc_in< bool > | clk |
sc_in< bool > | rd [CFG_MEMU_BANK_RAM_PORTS] |
sc_in< bool > | wr [CFG_MEMU_BANK_RAM_PORTS] |
sc_in< sc_uint< 4 > > | wen [CFG_MEMU_BANK_RAM_PORTS] |
sc_in< sc_uint< 32 > > | wiadr [CFG_MEMU_BANK_RAM_PORTS] |
sc_in< sc_uint< 32 > > | wdata [CFG_MEMU_BANK_RAM_PORTS] |
sc_out< sc_uint< 32 > > | rdata [CFG_MEMU_BANK_RAM_PORTS] |
Protected Attributes | |
sc_uint< 32 > | ram_ [CFG_MEMU_CACHE_SETS *CFG_MEMU_CACHE_WAYS] |
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inline |
void MBankRam::MainThread | ( | ) |
void MBankRam::Trace | ( | sc_trace_file * | tf, |
int | level = 1 |
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) |
sc_in<bool> MBankRam::clk |
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protected |
sc_in<bool> MBankRam::rd[CFG_MEMU_BANK_RAM_PORTS] |
sc_out<sc_uint<32> > MBankRam::rdata[CFG_MEMU_BANK_RAM_PORTS] |
sc_in<sc_uint<32> > MBankRam::wdata[CFG_MEMU_BANK_RAM_PORTS] |
sc_in<sc_uint<4> > MBankRam::wen[CFG_MEMU_BANK_RAM_PORTS] |
sc_in<sc_uint<32> > MBankRam::wiadr[CFG_MEMU_BANK_RAM_PORTS] |
sc_in<bool> MBankRam::wr[CFG_MEMU_BANK_RAM_PORTS] |