#include <interconnect.h>
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| MInterconnect (sc_module_name name) |
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void | Trace (sc_trace_file *tf, int level=1) |
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void | AddSlave (TWord start_adr, size_t size, MPeripheral *slave) |
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void | AddSlave (TWord start_adr, size_t size, sc_in_clk *wb_clk_i, sc_in< bool > *wb_rst_i, sc_in< bool > *wb_stb_i, sc_in< bool > *wb_cyc_i, sc_in< bool > *wb_we_i, sc_in< sc_uint< 3 > > *wb_cti_i, sc_in< sc_uint< 2 > > *wb_bte_i, sc_in< sc_uint< WB_PORT_SIZE/8 > > *wb_sel_i, sc_out< bool > *wb_ack_o, sc_out< bool > *wb_err_o, sc_out< bool > *wb_rty_o, sc_in< sc_uint< 32 > > *wb_adr_i, sc_in< sc_uint< WB_PORT_SIZE > > *wb_dat_i, sc_out< sc_uint< WB_PORT_SIZE > > *wb_dat_o) |
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void | InterconnectMethod () |
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◆ MInterconnect()
MInterconnect::MInterconnect |
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sc_module_name |
name | ) |
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inline |
◆ AddSlave() [1/2]
void MInterconnect::AddSlave |
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TWord |
start_adr, |
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size_t |
size, |
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MPeripheral * |
slave |
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) |
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◆ AddSlave() [2/2]
void MInterconnect::AddSlave |
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TWord |
start_adr, |
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size_t |
size, |
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sc_in_clk * |
wb_clk_i, |
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sc_in< bool > * |
wb_rst_i, |
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sc_in< bool > * |
wb_stb_i, |
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sc_in< bool > * |
wb_cyc_i, |
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sc_in< bool > * |
wb_we_i, |
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sc_in< sc_uint< 3 > > * |
wb_cti_i, |
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sc_in< sc_uint< 2 > > * |
wb_bte_i, |
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sc_in< sc_uint< WB_PORT_SIZE/8 > > * |
wb_sel_i, |
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sc_out< bool > * |
wb_ack_o, |
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sc_out< bool > * |
wb_err_o, |
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sc_out< bool > * |
wb_rty_o, |
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sc_in< sc_uint< 32 > > * |
wb_adr_i, |
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sc_in< sc_uint< WB_PORT_SIZE > > * |
wb_dat_i, |
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sc_out< sc_uint< WB_PORT_SIZE > > * |
wb_dat_o |
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) |
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◆ InterconnectMethod()
void MInterconnect::InterconnectMethod |
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◆ Trace()
void MInterconnect::Trace |
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sc_trace_file * |
tf, |
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int |
level = 1 |
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) |
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◆ ack_o
sc_out<bool> MInterconnect::ack_o |
◆ adr_i
sc_in<sc_uint<32> > MInterconnect::adr_i |
◆ bte_i
sc_out<sc_uint<2> > MInterconnect::bte_i |
◆ clk_i
sc_in_clk MInterconnect::clk_i |
◆ cti_i
sc_out<sc_uint<3> > MInterconnect::cti_i |
◆ cyc_i
sc_in<bool> MInterconnect::cyc_i |
◆ dat_i
◆ dat_o
◆ err_o
sc_out<bool> MInterconnect::err_o |
◆ rst_i
sc_in<bool> MInterconnect::rst_i |
◆ rty_o
sc_out<bool> MInterconnect::rty_o |
◆ sel_i
◆ stb_i
sc_in<bool> MInterconnect::stb_i |
◆ we_i
sc_in<bool> MInterconnect::we_i |
The documentation for this class was generated from the following files: