ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
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#include <memu.h>
Public Member Functions | |
MMemu (sc_module_name name) | |
~MMemu () | |
void | Trace (sc_trace_file *tf, int levels=1) |
void | TransitionMethod () |
void | InterconnectMethod () |
Protected Member Functions | |
void | InitSubmodules () |
void | FreeSubmodules () |
void | InitInterconnectMethod () |
Protected Attributes | |
sc_signal< bool > | tagram_ready |
sc_signal< bool > | tagram_rd [TR_PORTS] |
sc_signal< bool > | tagram_wr [TR_PORTS] |
sc_signal< sc_uint< 32 > > | tagram_adr [TR_PORTS] |
sc_signal< sc_uint< 32 > > | tagram_wadr [TR_PORTS] |
sc_signal< SCacheTag > | tagram_tag_in [TR_PORTS] |
sc_signal< SCacheTag > | tagram_tag_out [TR_PORTS] |
sc_signal< bool > | bankram_rd [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS] |
sc_signal< bool > | bankram_wr [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS] |
sc_signal< sc_uint< 4 > > | bankram_wen [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS] |
sc_signal< sc_uint< 32 > > | bankram_wiadr [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS] |
sc_signal< sc_uint< 32 > > | bankram_wdata [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS] |
sc_signal< sc_uint< 32 > > | bankram_rdata [CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS] |
sc_signal< bool > | master_cyc [MASTER_NO] |
sc_signal< bool > | master_stb [MASTER_NO] |
sc_signal< bool > | master_we [MASTER_NO] |
sc_signal< sc_uint< 3 > > | master_cti [MASTER_NO] |
sc_signal< sc_uint< 2 > > | master_bte [MASTER_NO] |
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > | master_sel [MASTER_NO] |
sc_signal< sc_uint< 32 > > | master_adr [MASTER_NO] |
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > | master_dat [MASTER_NO] |
sc_signal< bool > | switch_master |
sc_signal< EBusIfOperation > | busif_op |
sc_signal< bool > | busif_nolinelock |
sc_signal< bool > | busif_busy |
sc_signal< bool > | busif_tag_rd |
sc_signal< bool > | busif_tag_rd_way |
sc_signal< bool > | busif_tag_wr |
sc_signal< bool > | busif_bank_rd [CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | busif_bank_wr [CFG_MEMU_CACHE_BANKS] |
sc_signal< sc_uint< 32 > > | busif_adr_in |
sc_signal< sc_uint< 32 > > | busif_adr_out |
sc_signal< sc_uint< 32 > > | busif_data_in [CFG_MEMU_CACHE_BANKS] |
sc_signal< sc_uint< 32 > > | busif_data_out [CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | busif_data_out_valid [CFG_MEMU_CACHE_BANKS] |
sc_signal< SCacheTag > | busif_tag_in |
sc_signal< SCacheTag > | busif_tag_out |
sc_signal< sc_uint< 4 > > | busif_bsel |
sc_signal< bool > | busif_ac_r |
sc_signal< bool > | busif_ac_w |
sc_signal< bool > | busif_ac_x |
sc_signal< bool > | busif_ac_u |
sc_signal< bool > | busif_trap_u |
sc_signal< bool > | busif_trap_no_u |
sc_signal< bool > | busif_paging |
sc_signal< sc_uint< 32 > > | rp_busif_data_reg [CFG_MEMU_BUSIF_WIDTH/32] |
sc_signal< sc_uint< 32 > > | rp_busif_data [CFG_MEMU_RPORTS] |
sc_signal< EBusIfOperation > | rp_busif_op [CFG_MEMU_RPORTS] |
sc_signal< bool > | rp_tag_rd [CFG_MEMU_RPORTS] |
sc_signal< bool > | rp_bank_rd [CFG_MEMU_RPORTS] |
sc_signal< SCacheTag > | rp_tag_in [CFG_MEMU_RPORTS] |
sc_signal< sc_uint< 32 > > | rp_way_out [CFG_MEMU_RPORTS] |
sc_signal< sc_uint< 32 > > | rp_bank_data_in [CFG_MEMU_RPORTS] |
sc_signal< sc_uint< 32 > > | rp_bank_sel [CFG_MEMU_RPORTS] |
sc_signal< EBusIfOperation > | wp_busif_op [CFG_MEMU_WPORTS] |
sc_signal< bool > | wp_busif_nolinelock [CFG_MEMU_WPORTS] |
sc_signal< bool > | wp_tag_rd [CFG_MEMU_WPORTS] |
sc_signal< bool > | wp_tag_wr [CFG_MEMU_WPORTS] |
sc_signal< bool > | wp_bank_rd [CFG_MEMU_WPORTS] |
sc_signal< bool > | wp_bank_wr [CFG_MEMU_WPORTS] |
sc_signal< SCacheTag > | wp_tag_in [CFG_MEMU_WPORTS] |
sc_signal< SCacheTag > | wp_tag_out [CFG_MEMU_WPORTS] |
sc_signal< sc_uint< 32 > > | wp_bank_data_in [CFG_MEMU_WPORTS] |
sc_signal< sc_uint< 32 > > | wp_bank_data_out [CFG_MEMU_WPORTS] |
sc_signal< sc_uint< 4 > > | wp_bank_bsel [CFG_MEMU_WPORTS] |
sc_signal< bool > | req_busif_linelock |
sc_signal< bool > | req_wp_linelock [CFG_MEMU_WPORTS] |
sc_signal< bool > | gnt_busif_linelock |
sc_signal< bool > | gnt_wp_linelock [CFG_MEMU_WPORTS] |
sc_signal< bool > | req_busif_tagw |
sc_signal< bool > | req_wp_tagw [CFG_MEMU_WPORTS] |
sc_signal< bool > | req_busif_tagr |
sc_signal< bool > | req_wp_tagr [CFG_MEMU_WPORTS] |
sc_signal< bool > | req_rp_tagr [CFG_MEMU_RPORTS] |
sc_signal< bool > | gnt_busif_tagw |
sc_signal< bool > | gnt_wp_tagw [CFG_MEMU_WPORTS] |
sc_signal< bool > | gnt_busif_tagr |
sc_signal< bool > | gnt_wp_tagr [CFG_MEMU_WPORTS] |
sc_signal< bool > | gnt_rp_tagr [CFG_MEMU_RPORTS] |
sc_signal< bool > | gnt_busif_tagw_r |
sc_signal< bool > | gnt_wp_tagw_r [CFG_MEMU_WPORTS] |
sc_signal< bool > | gnt_busif_tagr_r |
sc_signal< bool > | gnt_wp_tagr_r [CFG_MEMU_WPORTS] |
sc_signal< bool > | gnt_rp_tagr_r [CFG_MEMU_RPORTS] |
sc_signal< bool > | req_busif_bank [CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | req_wp_bank [CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | req_rp_bank [CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | gnt_busif_bank [CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | gnt_wp_bank [CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | gnt_rp_bank [CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS] |
sc_signal< bool > | req_rp_busif [CFG_MEMU_RPORTS] |
sc_signal< bool > | gnt_rp_busif [CFG_MEMU_RPORTS] |
sc_signal< bool > | req_wp_busif [CFG_MEMU_WPORTS] |
sc_signal< bool > | gnt_wp_busif [CFG_MEMU_WPORTS] |
sc_signal< sc_uint< 32 > > | wiadr_busif |
sc_signal< sc_uint< 32 > > | wiadr_rp [CFG_MEMU_RPORTS] |
sc_signal< sc_uint< 32 > > | adr_wp [CFG_MEMU_WPORTS] |
sc_signal< sc_uint< 32 > > | way_wp [CFG_MEMU_WPORTS] |
sc_signal< sc_uint< 32 > > | snoop_adr |
sc_signal< bool > | snoop_stb [CFG_MEMU_WPORTS] |
sc_signal< sc_uint< 32 > > | ptw_phys_adr |
sc_signal< sc_uint< 32 > > | ptw_virt_adr |
sc_signal< bool > | ptw_req |
sc_signal< bool > | ptw_ack |
sc_signal< bool > | ptw_ac_r |
sc_signal< bool > | ptw_ac_w |
sc_signal< bool > | ptw_ac_x |
sc_signal< bool > | ptw_ac_u |
sc_signal< bool > | ptw_ac_d |
sc_signal< bool > | ptw_ac_a |
sc_signal< bool > | tlb_req |
sc_signal< bool > | tlb_wr |
sc_signal< sc_uint< 20 > > | tlb_va_o |
sc_signal< sc_uint< 20 > > | tlb_pa_o |
sc_signal< bool > | tlb_superpage_o |
sc_signal< bool > | tlb_ac_r_o |
sc_signal< bool > | tlb_ac_w_o |
sc_signal< bool > | tlb_ac_x_o |
sc_signal< bool > | tlb_ac_u_o |
sc_signal< bool > | tlb_ac_d_o |
sc_signal< bool > | tlb_ac_a_o |
sc_signal< bool > | tlb_superpage_i |
sc_signal< sc_uint< 20 > > | tlb_adr_i |
sc_signal< bool > | tlb_hit |
sc_signal< bool > | tlb_miss |
sc_signal< bool > | tlb_ac_r_i |
sc_signal< bool > | tlb_ac_w_i |
sc_signal< bool > | tlb_ac_x_i |
sc_signal< bool > | tlb_ac_u_i |
sc_signal< bool > | tlb_ac_d_i |
sc_signal< bool > | tlb_ac_a_i |
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void MMemu::InterconnectMethod | ( | ) |
void MMemu::Trace | ( | sc_trace_file * | tf, |
int | levels = 1 |
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void MMemu::TransitionMethod | ( | ) |
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MArbiter* MMemu::arbiter |
MBankRam* MMemu::bankRam[CFG_MEMU_CACHE_BANKS] |
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MBusController* MMemu::busController |
MBusIf* MMemu::busIf |
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sc_in<bool> MMemu::clk |
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MPtw* MMemu::ptw |
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MReadPort* MMemu::readPorts[CFG_MEMU_RPORTS] |
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sc_in<bool> MMemu::reset |
sc_in<sc_uint<20> > MMemu::root_ppn |
sc_out<bool> MMemu::rp_ac_r[CFG_MEMU_RPORTS] |
sc_out<bool> MMemu::rp_ac_u[CFG_MEMU_RPORTS] |
sc_out<bool> MMemu::rp_ac_x[CFG_MEMU_RPORTS] |
sc_out<bool> MMemu::rp_ack[CFG_MEMU_RPORTS] |
sc_in<sc_uint<32> > MMemu::rp_adr[CFG_MEMU_RPORTS] |
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sc_in<sc_uint<4> > MMemu::rp_bsel[CFG_MEMU_RPORTS] |
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sc_out<sc_uint<32> > MMemu::rp_data[CFG_MEMU_RPORTS] |
sc_in<bool> MMemu::rp_direct[CFG_MEMU_RPORTS] |
sc_in<bool> MMemu::rp_paging[CFG_MEMU_RPORTS] |
sc_in<bool> MMemu::rp_rd[CFG_MEMU_RPORTS] |
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MTagRam* MMemu::tagRam |
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MTlb* MMemu::tlb |
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sc_in<bool> MMemu::tlb_flush |
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sc_in<bool> MMemu::wb_ack_i |
sc_out<sc_uint<32> > MMemu::wb_adr_o |
sc_out<sc_uint<2> > MMemu::wb_bte_o |
sc_out<sc_uint<3> > MMemu::wb_cti_o |
sc_out<bool> MMemu::wb_cyc_o |
sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MMemu::wb_dat_i |
sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MMemu::wb_dat_o |
sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > MMemu::wb_sel_o |
sc_out<bool> MMemu::wb_stb_o |
sc_out<bool> MMemu::wb_we_o |
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sc_out<bool> MMemu::wp_ac_w[CFG_MEMU_WPORTS] |
sc_out<bool> MMemu::wp_ack[CFG_MEMU_WPORTS] |
sc_in<sc_uint<32> > MMemu::wp_adr[CFG_MEMU_WPORTS] |
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sc_in<sc_uint<4> > MMemu::wp_bsel[CFG_MEMU_WPORTS] |
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sc_in<sc_uint<3> > MMemu::wp_cache_op[CFG_MEMU_WPORTS] |
sc_in<sc_uint<32> > MMemu::wp_data[CFG_MEMU_WPORTS] |
sc_in<bool> MMemu::wp_direct[CFG_MEMU_WPORTS] |
sc_in<bool> MMemu::wp_lres_scond[CFG_MEMU_WPORTS] |
sc_in<bool> MMemu::wp_paging[CFG_MEMU_WPORTS] |
sc_out<bool> MMemu::wp_scond_ok[CFG_MEMU_WPORTS] |
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sc_in<bool> MMemu::wp_trap_no_u[CFG_MEMU_WPORTS] |
sc_in<bool> MMemu::wp_trap_u[CFG_MEMU_WPORTS] |
sc_in<bool> MMemu::wp_wr[CFG_MEMU_WPORTS] |
MWritePort* MMemu::writePorts[CFG_MEMU_WPORTS] |