ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
Public Member Functions | Public Attributes | Protected Member Functions | Protected Attributes | List of all members
MParanut Class Reference

#include <nut.h>

Inheritance diagram for MParanut:
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Collaboration diagram for MParanut:
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Public Member Functions

 MParanut (sc_module_name name)
 
 ~MParanut ()
 
void Trace (sc_trace_file *tf, int levels=1)
 
void DisplayStatistics (const int num=0)
 
bool IsHalted ()
 
void InterconnectMethod ()
 

Public Attributes

sc_in< bool > clk_i
 
sc_in< bool > rst_i
 
sc_out< bool > cyc_o
 
sc_out< bool > stb_o
 
sc_out< bool > we_o
 
sc_out< sc_uint< 3 > > cti_o
 
sc_out< sc_uint< 2 > > bte_o
 
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > sel_o
 
sc_in< bool > ack_i
 
sc_in< bool > err_i
 
sc_in< bool > rty_i
 
sc_out< sc_uint< 32 > > adr_o
 
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_i
 
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_o
 
sc_in< bool > ex_int [CFG_NUT_EX_INT]
 
sc_in< bool > tck
 
sc_in< bool > tms
 
sc_in< bool > tdi
 
sc_out< bool > tdo
 
MMemumemu
 
MDebugModuledm
 
MDtmdtm
 
MIntCintc
 
MIfuifu [CFG_NUT_CPU_CAP2_CORES]
 
MCsr * csr [CFG_NUT_CPU_CORES]
 
MExuexu [CFG_NUT_CPU_CORES]
 
MLsulsu [CFG_NUT_CPU_CORES]
 
Mtimermtimer
 

Protected Member Functions

void InitSubmodules ()
 
void FreeSubmodules ()
 
void InitInterconnectMethod ()
 

Protected Attributes

sc_signal< bool > rp_rd [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_direct [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_paging [2 *CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 4 > > rp_bsel [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_ack [2 *CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > rp_adr [2 *CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > rp_data [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_ac_r [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_ac_x [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_ac_u [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_trap_u [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > rp_trap_no_u [2 *CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_wr [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_direct [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_paging [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 4 > > wp_bsel [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_ack [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_lres_scond [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_scond_ok [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 3 > > wp_cache_op [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > wp_adr [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > wp_data [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_ac_w [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_trap_u [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wp_trap_no_u [CFG_NUT_CPU_CORES]
 
sc_signal< bool > wb_ack
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat
 
sc_signal< bool > ifu_next [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > ifu_jump [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > ifu_flush [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > ifu_reset [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > ifu_jump_adr [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > ifu_ir_valid [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > ifu_npc_valid [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< sc_uint< 32 > > ifu_ir [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< sc_uint< 32 > > ifu_pc [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< sc_uint< 32 > > ifu_npc [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > ifu_ac_x [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > ifu_ac_u [CFG_NUT_CPU_CAP2_CORES]
 
sc_signal< bool > lsu_rd [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_wr [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_flush [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_trap_u [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_trap_no_u [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_ac_r [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_ac_w [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_ac_u [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_lres_scond [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 3 > > lsu_cache_op [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_ack [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_align_err [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_scond_ok [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 2 > > lsu_width [CFG_NUT_CPU_CORES]
 
sc_signal< bool > lsu_exts [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > lsu_adr [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > lsu_rdata [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > lsu_wdata [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnce
 
sc_signal< sc_uint< 2 > > m3_priv_mode
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnlm
 
sc_signal< sc_uint< 32 > > cepu_pnifadr
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnifadren
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnxsel
 
sc_signal< bool > m3_ir_request
 
sc_signal< sc_uint< 5 > > m3_ir_id
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnhaltreq
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnx
 
sc_signal< bool > m3_ex_i
 
sc_signal< bool > m3_icache_enable
 
sc_signal< bool > m3_dcache_enable
 
sc_signal< bool > m3_ir_ack
 
sc_signal< bool > m3_ir_enable
 
sc_signal< bool > mtimer_ack_i
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > mtimer_dat_i
 
sc_signal< bool > mtimer_ir_request
 
sc_signal< bool > mtimer_irq_enable_in
 
sc_signal< bool > csr_mtip_in
 
sc_signal< bool > exu_haltreq [CFG_NUT_CPU_CORES]
 
sc_signal< bool > exu_enable [CFG_NUT_CPU_CORES]
 
sc_signal< bool > exu_ifu_reset [CFG_NUT_CPU_CORES]
 
sc_signal< bool > exu_linked [CFG_NUT_CPU_CORES]
 
sc_signal< bool > exu_ex_o [CFG_NUT_CPU_CORES]
 
sc_signal< bool > exu_xsel [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 5 > > exu_cause [CFG_NUT_CPU_CORES - 1]
 
sc_signal< bool > exu_sync [CFG_NUT_CPU_CORES]
 
sc_signal< bool > exu_dbg_req [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > dbg_req
 
sc_signal< bool > dbg_reset
 
sc_signal< bool > dbg_ack_i
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dbg_dat_i
 
sc_signal< sc_uint< DTM_ADDR_WIDTH > > dmi_adr
 
sc_signal< sc_uint< 32 > > dmi_dat_o
 
sc_signal< sc_uint< 32 > > dmi_dat_i
 
sc_signal< bool > dmi_rd
 
sc_signal< bool > dmi_wr
 
sc_signal< sc_uint< 32 > > csr_pc [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_ir [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES_LD > > csr_hartID [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_inCePU [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_linked [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_cpu_enabled [CFG_NUT_CPU_CORES]
 
sc_signal< bool > dbg [CFG_NUT_CPU_CORES]
 
sc_signal< bool > dbg_reg [CFG_NUT_CPU_CORES]
 
sc_signal< bool > dbg_enter_dreg [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_enable [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 5 > > ex_id_reg [CFG_NUT_CPU_CORES]
 
sc_signal< bool > sret_dreg [CFG_NUT_CPU_CORES]
 
sc_signal< bool > exception [CFG_NUT_CPU_CORES]
 
sc_signal< bool > irq_dreg [CFG_NUT_CPU_CORES]
 
sc_signal< bool > pop_priv_ir_stack_dreg [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 5 > > csr_rs1_reg [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_op_a [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 3 > > csr_function_reg [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 12 > > csr_adr_reg [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_tval [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnce [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnlm [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnxsel [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 2 > > csr_m3_priv_mode [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_m3_icache_enable [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_m3_dcache_enable [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_isHalted [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 2 > > priv_mode [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 2 > > load_store_priv_mode [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_mstatus_MIE [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_mstatus_SIE [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_mstatus_TSR [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_mstatus_SUM [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_mstatus_TVM [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_sepc [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_stvec [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_mideleg [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_mip [CFG_NUT_CPU_CORES]
 
sc_signal< bool > delegate_dreg [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_exception [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_dcsr_step [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_dcsr_ebreakm [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_mepc [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_dpc [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_mtvec [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_mcause [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 32 > > csr_rdata [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 5 > > csr_cause [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_ack [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_cache_flush [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnhaltreq [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnx [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_ifu_paging_mode [CFG_NUT_CPU_CORES]
 
sc_signal< bool > csr_lsu_paging_mode [CFG_NUT_CPU_CORES]
 
sc_signal< bool > ifu_paging_mode
 
sc_signal< bool > lsu_paging_mode
 
sc_signal< sc_uint< 20 > > root_ppn
 
sc_signal< bool > csr_satp_mode [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< 20 > > csr_satp_root_ppn [CFG_NUT_CPU_CORES]
 
sc_signal< bool > tlb_flush
 
sc_signal< bool > perf_inc [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_EXU_PERFCOUNTERS_LD > > perf_addr [CFG_NUT_CPU_CORES]
 
sc_signal< sc_uint< CFG_NUT_EX_INT > > intc_ex_int
 
sc_signal< bool > csr_mip_MTIP
 
sc_signal< bool > csr_mip_MEIP
 
sc_signal< bool > reset
 

Constructor & Destructor Documentation

◆ MParanut()

MParanut::MParanut ( sc_module_name  name)
inline

◆ ~MParanut()

MParanut::~MParanut ( )
inline

Member Function Documentation

◆ DisplayStatistics()

void MParanut::DisplayStatistics ( const int  num = 0)
inline

◆ FreeSubmodules()

void MParanut::FreeSubmodules ( )
protected

◆ InitInterconnectMethod()

void MParanut::InitInterconnectMethod ( )
protected

◆ InitSubmodules()

void MParanut::InitSubmodules ( )
protected

◆ InterconnectMethod()

void MParanut::InterconnectMethod ( )

◆ IsHalted()

bool MParanut::IsHalted ( )
inline

◆ Trace()

void MParanut::Trace ( sc_trace_file *  tf,
int  levels = 1 
)

Member Data Documentation

◆ ack_i

sc_in<bool> MParanut::ack_i

◆ adr_o

sc_out<sc_uint<32> > MParanut::adr_o

◆ bte_o

sc_out<sc_uint<2> > MParanut::bte_o

◆ cepu_pnifadr

sc_signal<sc_uint<32> > MParanut::cepu_pnifadr
protected

◆ clk_i

sc_in<bool> MParanut::clk_i

◆ csr

MCsr* MParanut::csr[CFG_NUT_CPU_CORES]

◆ csr_ack

sc_signal<bool> MParanut::csr_ack[CFG_NUT_CPU_CORES]
protected

◆ csr_adr_reg

sc_signal<sc_uint<12> > MParanut::csr_adr_reg[CFG_NUT_CPU_CORES]
protected

◆ csr_cache_flush

sc_signal<bool> MParanut::csr_cache_flush[CFG_NUT_CPU_CORES]
protected

◆ csr_cause

sc_signal<sc_uint<5> > MParanut::csr_cause[CFG_NUT_CPU_CORES]
protected

◆ csr_cpu_enabled

sc_signal<bool> MParanut::csr_cpu_enabled[CFG_NUT_CPU_CORES]
protected

◆ csr_dcsr_ebreakm

sc_signal<bool> MParanut::csr_dcsr_ebreakm[CFG_NUT_CPU_CORES]
protected

◆ csr_dcsr_step

sc_signal<bool> MParanut::csr_dcsr_step[CFG_NUT_CPU_CORES]
protected

◆ csr_dpc

sc_signal<sc_uint<32> > MParanut::csr_dpc[CFG_NUT_CPU_CORES]
protected

◆ csr_enable

sc_signal<bool> MParanut::csr_enable[CFG_NUT_CPU_CORES]
protected

◆ csr_exception

sc_signal<bool> MParanut::csr_exception[CFG_NUT_CPU_CORES]
protected

◆ csr_function_reg

sc_signal<sc_uint<3> > MParanut::csr_function_reg[CFG_NUT_CPU_CORES]
protected

◆ csr_hartID

sc_signal<sc_uint<CFG_NUT_CPU_CORES_LD> > MParanut::csr_hartID[CFG_NUT_CPU_CORES]
protected

◆ csr_ifu_paging_mode

sc_signal<bool> MParanut::csr_ifu_paging_mode[CFG_NUT_CPU_CORES]
protected

◆ csr_inCePU

sc_signal<bool> MParanut::csr_inCePU[CFG_NUT_CPU_CORES]
protected

◆ csr_ir

sc_signal<sc_uint<32> > MParanut::csr_ir[CFG_NUT_CPU_CORES]
protected

◆ csr_isHalted

sc_signal<bool> MParanut::csr_isHalted[CFG_NUT_CPU_CORES]
protected

◆ csr_linked

sc_signal<bool> MParanut::csr_linked[CFG_NUT_CPU_CORES]
protected

◆ csr_lsu_paging_mode

sc_signal<bool> MParanut::csr_lsu_paging_mode[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_dcache_enable

sc_signal<bool> MParanut::csr_m3_dcache_enable[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_icache_enable

sc_signal<bool> MParanut::csr_m3_icache_enable[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_pnce

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::csr_m3_pnce[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_pnhaltreq

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::csr_m3_pnhaltreq[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_pnlm

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::csr_m3_pnlm[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_pnx

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::csr_m3_pnx[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_pnxsel

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::csr_m3_pnxsel[CFG_NUT_CPU_CORES]
protected

◆ csr_m3_priv_mode

sc_signal<sc_uint<2> > MParanut::csr_m3_priv_mode[CFG_NUT_CPU_CORES]
protected

◆ csr_mcause

sc_signal<sc_uint<32> > MParanut::csr_mcause[CFG_NUT_CPU_CORES]
protected

◆ csr_mepc

sc_signal<sc_uint<32> > MParanut::csr_mepc[CFG_NUT_CPU_CORES]
protected

◆ csr_mideleg

sc_signal<sc_uint<32> > MParanut::csr_mideleg[CFG_NUT_CPU_CORES]
protected

◆ csr_mip

sc_signal<sc_uint<32> > MParanut::csr_mip[CFG_NUT_CPU_CORES]
protected

◆ csr_mip_MEIP

sc_signal<bool> MParanut::csr_mip_MEIP
protected

◆ csr_mip_MTIP

sc_signal<bool> MParanut::csr_mip_MTIP
protected

◆ csr_mstatus_MIE

sc_signal<bool> MParanut::csr_mstatus_MIE[CFG_NUT_CPU_CORES]
protected

◆ csr_mstatus_SIE

sc_signal<bool> MParanut::csr_mstatus_SIE[CFG_NUT_CPU_CORES]
protected

◆ csr_mstatus_SUM

sc_signal<bool> MParanut::csr_mstatus_SUM[CFG_NUT_CPU_CORES]
protected

◆ csr_mstatus_TSR

sc_signal<bool> MParanut::csr_mstatus_TSR[CFG_NUT_CPU_CORES]
protected

◆ csr_mstatus_TVM

sc_signal<bool> MParanut::csr_mstatus_TVM[CFG_NUT_CPU_CORES]
protected

◆ csr_mtip_in

sc_signal<bool> MParanut::csr_mtip_in
protected

◆ csr_mtvec

sc_signal<sc_uint<32> > MParanut::csr_mtvec[CFG_NUT_CPU_CORES]
protected

◆ csr_op_a

sc_signal<sc_uint<32> > MParanut::csr_op_a[CFG_NUT_CPU_CORES]
protected

◆ csr_pc

sc_signal<sc_uint<32> > MParanut::csr_pc[CFG_NUT_CPU_CORES]
protected

◆ csr_rdata

sc_signal<sc_uint<32> > MParanut::csr_rdata[CFG_NUT_CPU_CORES]
protected

◆ csr_rs1_reg

sc_signal<sc_uint<5> > MParanut::csr_rs1_reg[CFG_NUT_CPU_CORES]
protected

◆ csr_satp_mode

sc_signal<bool> MParanut::csr_satp_mode[CFG_NUT_CPU_CORES]
protected

◆ csr_satp_root_ppn

sc_signal<sc_uint<20> > MParanut::csr_satp_root_ppn[CFG_NUT_CPU_CORES]
protected

◆ csr_sepc

sc_signal<sc_uint<32> > MParanut::csr_sepc[CFG_NUT_CPU_CORES]
protected

◆ csr_stvec

sc_signal<sc_uint<32> > MParanut::csr_stvec[CFG_NUT_CPU_CORES]
protected

◆ csr_tval

sc_signal<sc_uint<32> > MParanut::csr_tval[CFG_NUT_CPU_CORES]
protected

◆ cti_o

sc_out<sc_uint<3> > MParanut::cti_o

◆ cyc_o

sc_out<bool> MParanut::cyc_o

◆ dat_i

sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MParanut::dat_i

◆ dat_o

sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MParanut::dat_o

◆ dbg

sc_signal<bool> MParanut::dbg[CFG_NUT_CPU_CORES]
protected

◆ dbg_ack_i

sc_signal<bool> MParanut::dbg_ack_i
protected

◆ dbg_dat_i

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MParanut::dbg_dat_i
protected

◆ dbg_enter_dreg

sc_signal<bool> MParanut::dbg_enter_dreg[CFG_NUT_CPU_CORES]
protected

◆ dbg_reg

sc_signal<bool> MParanut::dbg_reg[CFG_NUT_CPU_CORES]
protected

◆ dbg_req

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::dbg_req
protected

◆ dbg_reset

sc_signal<bool> MParanut::dbg_reset
protected

◆ delegate_dreg

sc_signal<bool> MParanut::delegate_dreg[CFG_NUT_CPU_CORES]
protected

◆ dm

MDebugModule* MParanut::dm

◆ dmi_adr

sc_signal<sc_uint<DTM_ADDR_WIDTH> > MParanut::dmi_adr
protected

◆ dmi_dat_i

sc_signal<sc_uint<32> > MParanut::dmi_dat_i
protected

◆ dmi_dat_o

sc_signal<sc_uint<32> > MParanut::dmi_dat_o
protected

◆ dmi_rd

sc_signal<bool> MParanut::dmi_rd
protected

◆ dmi_wr

sc_signal<bool> MParanut::dmi_wr
protected

◆ dtm

MDtm* MParanut::dtm

◆ err_i

sc_in<bool> MParanut::err_i

◆ ex_id_reg

sc_signal<sc_uint<5> > MParanut::ex_id_reg[CFG_NUT_CPU_CORES]
protected

◆ ex_int

sc_in<bool> MParanut::ex_int[CFG_NUT_EX_INT]

◆ exception

sc_signal<bool> MParanut::exception[CFG_NUT_CPU_CORES]
protected

◆ exu

MExu* MParanut::exu[CFG_NUT_CPU_CORES]

◆ exu_cause

sc_signal<sc_uint<5> > MParanut::exu_cause[CFG_NUT_CPU_CORES - 1]
protected

◆ exu_dbg_req

sc_signal<bool> MParanut::exu_dbg_req[CFG_NUT_CPU_CORES]
protected

◆ exu_enable

sc_signal<bool> MParanut::exu_enable[CFG_NUT_CPU_CORES]
protected

◆ exu_ex_o

sc_signal<bool> MParanut::exu_ex_o[CFG_NUT_CPU_CORES]
protected

◆ exu_haltreq

sc_signal<bool> MParanut::exu_haltreq[CFG_NUT_CPU_CORES]
protected

◆ exu_ifu_reset

sc_signal<bool> MParanut::exu_ifu_reset[CFG_NUT_CPU_CORES]
protected

◆ exu_linked

sc_signal<bool> MParanut::exu_linked[CFG_NUT_CPU_CORES]
protected

◆ exu_sync

sc_signal<bool> MParanut::exu_sync[CFG_NUT_CPU_CORES]
protected

◆ exu_xsel

sc_signal<bool> MParanut::exu_xsel[CFG_NUT_CPU_CORES]
protected

◆ ifu

MIfu* MParanut::ifu[CFG_NUT_CPU_CAP2_CORES]

◆ ifu_ac_u

sc_signal<bool> MParanut::ifu_ac_u[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_ac_x

sc_signal<bool> MParanut::ifu_ac_x[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_flush

sc_signal<bool> MParanut::ifu_flush[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_ir

sc_signal<sc_uint<32> > MParanut::ifu_ir[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_ir_valid

sc_signal<bool> MParanut::ifu_ir_valid[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_jump

sc_signal<bool> MParanut::ifu_jump[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_jump_adr

sc_signal<sc_uint<32> > MParanut::ifu_jump_adr[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_next

sc_signal<bool> MParanut::ifu_next[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_npc

sc_signal<sc_uint<32> > MParanut::ifu_npc[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_npc_valid

sc_signal<bool> MParanut::ifu_npc_valid[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_paging_mode

sc_signal<bool> MParanut::ifu_paging_mode
protected

◆ ifu_pc

sc_signal<sc_uint<32> > MParanut::ifu_pc[CFG_NUT_CPU_CAP2_CORES]
protected

◆ ifu_reset

sc_signal<bool> MParanut::ifu_reset[CFG_NUT_CPU_CORES]
protected

◆ intc

MIntC* MParanut::intc

◆ intc_ex_int

sc_signal<sc_uint<CFG_NUT_EX_INT> > MParanut::intc_ex_int
protected

◆ irq_dreg

sc_signal<bool> MParanut::irq_dreg[CFG_NUT_CPU_CORES]
protected

◆ load_store_priv_mode

sc_signal<sc_uint<2> > MParanut::load_store_priv_mode[CFG_NUT_CPU_CORES]
protected

◆ lsu

MLsu* MParanut::lsu[CFG_NUT_CPU_CORES]

◆ lsu_ac_r

sc_signal<bool> MParanut::lsu_ac_r[CFG_NUT_CPU_CORES]
protected

◆ lsu_ac_u

sc_signal<bool> MParanut::lsu_ac_u[CFG_NUT_CPU_CORES]
protected

◆ lsu_ac_w

sc_signal<bool> MParanut::lsu_ac_w[CFG_NUT_CPU_CORES]
protected

◆ lsu_ack

sc_signal<bool> MParanut::lsu_ack[CFG_NUT_CPU_CORES]
protected

◆ lsu_adr

sc_signal<sc_uint<32> > MParanut::lsu_adr[CFG_NUT_CPU_CORES]
protected

◆ lsu_align_err

sc_signal<bool> MParanut::lsu_align_err[CFG_NUT_CPU_CORES]
protected

◆ lsu_cache_op

sc_signal<sc_uint<3> > MParanut::lsu_cache_op[CFG_NUT_CPU_CORES]
protected

◆ lsu_exts

sc_signal<bool> MParanut::lsu_exts[CFG_NUT_CPU_CORES]
protected

◆ lsu_flush

sc_signal<bool> MParanut::lsu_flush[CFG_NUT_CPU_CORES]
protected

◆ lsu_lres_scond

sc_signal<bool> MParanut::lsu_lres_scond[CFG_NUT_CPU_CORES]
protected

◆ lsu_paging_mode

sc_signal<bool> MParanut::lsu_paging_mode
protected

◆ lsu_rd

sc_signal<bool> MParanut::lsu_rd[CFG_NUT_CPU_CORES]
protected

◆ lsu_rdata

sc_signal<sc_uint<32> > MParanut::lsu_rdata[CFG_NUT_CPU_CORES]
protected

◆ lsu_scond_ok

sc_signal<bool> MParanut::lsu_scond_ok[CFG_NUT_CPU_CORES]
protected

◆ lsu_trap_no_u

sc_signal<bool> MParanut::lsu_trap_no_u[CFG_NUT_CPU_CORES]
protected

◆ lsu_trap_u

sc_signal<bool> MParanut::lsu_trap_u[CFG_NUT_CPU_CORES]
protected

◆ lsu_wdata

sc_signal<sc_uint<32> > MParanut::lsu_wdata[CFG_NUT_CPU_CORES]
protected

◆ lsu_width

sc_signal<sc_uint<2> > MParanut::lsu_width[CFG_NUT_CPU_CORES]
protected

◆ lsu_wr

sc_signal<bool> MParanut::lsu_wr[CFG_NUT_CPU_CORES]
protected

◆ m3_dcache_enable

sc_signal<bool> MParanut::m3_dcache_enable
protected

◆ m3_ex_i

sc_signal<bool> MParanut::m3_ex_i
protected

◆ m3_icache_enable

sc_signal<bool> MParanut::m3_icache_enable
protected

◆ m3_ir_ack

sc_signal<bool> MParanut::m3_ir_ack
protected

◆ m3_ir_enable

sc_signal<bool> MParanut::m3_ir_enable
protected

◆ m3_ir_id

sc_signal<sc_uint<5> > MParanut::m3_ir_id
protected

◆ m3_ir_request

sc_signal<bool> MParanut::m3_ir_request
protected

◆ m3_pnce

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::m3_pnce
protected

◆ m3_pnhaltreq

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::m3_pnhaltreq
protected

◆ m3_pnifadren

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::m3_pnifadren
protected

◆ m3_pnlm

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::m3_pnlm
protected

◆ m3_pnx

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::m3_pnx
protected

◆ m3_pnxsel

sc_signal<sc_uint<CFG_NUT_CPU_CORES> > MParanut::m3_pnxsel
protected

◆ m3_priv_mode

sc_signal<sc_uint<2> > MParanut::m3_priv_mode
protected

◆ memu

MMemu* MParanut::memu

◆ mtimer

Mtimer* MParanut::mtimer

◆ mtimer_ack_i

sc_signal<bool> MParanut::mtimer_ack_i
protected

◆ mtimer_dat_i

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MParanut::mtimer_dat_i
protected

◆ mtimer_ir_request

sc_signal<bool> MParanut::mtimer_ir_request
protected

◆ mtimer_irq_enable_in

sc_signal<bool> MParanut::mtimer_irq_enable_in
protected

◆ perf_addr

sc_signal<sc_uint<CFG_EXU_PERFCOUNTERS_LD> > MParanut::perf_addr[CFG_NUT_CPU_CORES]
protected

◆ perf_inc

sc_signal<bool> MParanut::perf_inc[CFG_NUT_CPU_CORES]
protected

◆ pop_priv_ir_stack_dreg

sc_signal<bool> MParanut::pop_priv_ir_stack_dreg[CFG_NUT_CPU_CORES]
protected

◆ priv_mode

sc_signal<sc_uint<2> > MParanut::priv_mode[CFG_NUT_CPU_CORES]
protected

◆ reset

sc_signal<bool> MParanut::reset
protected

◆ root_ppn

sc_signal<sc_uint<20> > MParanut::root_ppn
protected

◆ rp_ac_r

sc_signal<bool> MParanut::rp_ac_r[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_ac_u

sc_signal<bool> MParanut::rp_ac_u[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_ac_x

sc_signal<bool> MParanut::rp_ac_x[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_ack

sc_signal<bool> MParanut::rp_ack[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_adr

sc_signal<sc_uint<32> > MParanut::rp_adr[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_bsel

sc_signal<sc_uint<4> > MParanut::rp_bsel[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_data

sc_signal<sc_uint<32> > MParanut::rp_data[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_direct

sc_signal<bool> MParanut::rp_direct[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_paging

sc_signal<bool> MParanut::rp_paging[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_rd

sc_signal<bool> MParanut::rp_rd[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_trap_no_u

sc_signal<bool> MParanut::rp_trap_no_u[2 *CFG_NUT_CPU_CORES]
protected

◆ rp_trap_u

sc_signal<bool> MParanut::rp_trap_u[2 *CFG_NUT_CPU_CORES]
protected

◆ rst_i

sc_in<bool> MParanut::rst_i

◆ rty_i

sc_in<bool> MParanut::rty_i

◆ sel_o

sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > MParanut::sel_o

◆ sret_dreg

sc_signal<bool> MParanut::sret_dreg[CFG_NUT_CPU_CORES]
protected

◆ stb_o

sc_out<bool> MParanut::stb_o

◆ tck

sc_in<bool> MParanut::tck

◆ tdi

sc_in<bool> MParanut::tdi

◆ tdo

sc_out<bool> MParanut::tdo

◆ tlb_flush

sc_signal<bool> MParanut::tlb_flush
protected

◆ tms

sc_in<bool> MParanut::tms

◆ wb_ack

sc_signal<bool> MParanut::wb_ack
protected

◆ wb_dat

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > MParanut::wb_dat
protected

◆ we_o

sc_out<bool> MParanut::we_o

◆ wp_ac_w

sc_signal<bool> MParanut::wp_ac_w[CFG_NUT_CPU_CORES]
protected

◆ wp_ack

sc_signal<bool> MParanut::wp_ack[CFG_NUT_CPU_CORES]
protected

◆ wp_adr

sc_signal<sc_uint<32> > MParanut::wp_adr[CFG_NUT_CPU_CORES]
protected

◆ wp_bsel

sc_signal<sc_uint<4> > MParanut::wp_bsel[CFG_NUT_CPU_CORES]
protected

◆ wp_cache_op

sc_signal<sc_uint<3> > MParanut::wp_cache_op[CFG_NUT_CPU_CORES]
protected

◆ wp_data

sc_signal<sc_uint<32> > MParanut::wp_data[CFG_NUT_CPU_CORES]
protected

◆ wp_direct

sc_signal<bool> MParanut::wp_direct[CFG_NUT_CPU_CORES]
protected

◆ wp_lres_scond

sc_signal<bool> MParanut::wp_lres_scond[CFG_NUT_CPU_CORES]
protected

◆ wp_paging

sc_signal<bool> MParanut::wp_paging[CFG_NUT_CPU_CORES]
protected

◆ wp_scond_ok

sc_signal<bool> MParanut::wp_scond_ok[CFG_NUT_CPU_CORES]
protected

◆ wp_trap_no_u

sc_signal<bool> MParanut::wp_trap_no_u[CFG_NUT_CPU_CORES]
protected

◆ wp_trap_u

sc_signal<bool> MParanut::wp_trap_u[CFG_NUT_CPU_CORES]
protected

◆ wp_wr

sc_signal<bool> MParanut::wp_wr[CFG_NUT_CPU_CORES]
protected

The documentation for this class was generated from the following files: