ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
csr.h
Go to the documentation of this file.
1 /*************************************************************************
2 
3  This file is part of the ParaNut project.
4 
5  Copyright (C) 2010-2022 Alexander Bahle <alexander.bahle@hs-augsburg.de>
6  Christian H. Meyer <christian.meyer@hs-augsburg.de>
7  Gundolf Kiefer <gundolf.kiefer@hs-augsburg.de>
8  Nico Borgsmüller <nico.borgsmueller@hs-augsburg.de>
9  Hochschule Augsburg, University of Applied Sciences
10 
11  Description:
12  This is a SystemC model of the CSR module (CSR) of the ParaNut.
13  When accessing an CSR from the EXU, the methods of this module
14  are called. It is used as a submodule of the EXU.
15 
16  Redistribution and use in source and binary forms, with or without modification,
17  are permitted provided that the following conditions are met:
18 
19  1. Redistributions of source code must retain the above copyright notice, this
20  list of conditions and the following disclaimer.
21 
22  2. Redistributions in binary form must reproduce the above copyright notice,
23  this list of conditions and the following disclaimer in the documentation and/or
24  other materials provided with the distribution.
25 
26  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
27  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
30  ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
33  ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 
37  *************************************************************************/
38 
39 #pragma once
40 
41 #include "paranut-peripheral.h"
42 
43 #include "base.h"
44 #include "paranut-config.h"
45 #include "exu_csr.h"
46 
47 #if CFG_EXU_PERFCOUNT_ENABLE == 1
48 #define CYCLEREG_LOW (csr_mcycle.read () (31, 0))
49 #define CYCLEREG_HIGH (csr_mcycle.read () (63, 32))
50 #define PERFREGS(COUNTER) csr_mhpmcounter[COUNTER].read ()
51 #else // CFG_EXU_PERFCOUNT_ENABLE != 1
52 #define PERFREGS(COUNTER) sc_uint<CFG_EXU_PERFCOUNTER_BITS> (0x0)
53 #define CYCLEREG_LOW 0x0
54 #define CYCLEREG_HIGH 0x0
55 #endif
56 // **************** CSR Function Codes *************
57 typedef enum {
58  CSRRW = 1,
61 } ECSRFunc;
62 
63 // **************** Special Registers ***********
64 typedef enum {
65  // Machine Information Registers
66  mvendorid = 0xF11,
70 
71  // Machine Trap Setup
72  mstatus = 0x300,
74  medeleg, // medeleg and mideleg may only exist if S-Mode
75  mideleg, // or N-Extension are available
76  mie,
78 
79  // Machine Trap Handling
80  mscratch = 0x340,
84  mip,
85 
86  // Machine Counter/Timers
87  mcycle = 0xB00,
88  minstret = 0xB02,
95  //... todo: implement 9 ... 30
96  mhpmcounter31 = 0xB1F,
97  mcycleh = 0xB80,
98  minstreth = 0xB82,
105  //... todo: implement 9 ... 30
106  mhpmcounter31h = 0xB9F,
107 
108  // Machine Counter Setup
109  mhpmevent3 = 0x323,
110  //... todo: implement 4 ... 30
111  mhpmevent31 = 0x33F,
112 
113  // Supervisor Trap Setup
114  sstatus = 0x100,
115  sedeleg = 0x102,
120 
121  // Supervisor Trap Handling
122  sscratch = 0x140,
127 
128  // Supervisor Protection and Translation
129  satp = 0x180,
130 
131  // User Trap Setup
132  ustatus = 0x000,
133  uie = 0x004,
135 
136  // User Trap Handling
137  uscratch = 0x040,
142 
143  // User Counter/Timers
144  ucycle = 0xC00,
208 
209  // Debug
210  dcsr = 0x7b0,
213  tselect = 0x7a0,
214 
215  // Non-Standard machine read/write paranut:
216  pncache = 0x7C0,
217 
218  // Non-Standard user read/write paranut:
219  pngrpsel = 0x8C0,
223 
224  // Non-Standard machine read-only paranut:
225  pnm2cp = 0xFC0,
227  pncacheinfo = 0xFC4,
233 
234  // Non-Standard user read-only paranut:
235  pncpus = 0xCD0,
236  pncoreid = 0xCD4,
237 
238  // Non-Standard User read/write paranut:
239  pnepc = 0x841,
240  pncause = 0x842,
241 } ECSR;
242 
243 
244 SC_MODULE (MCsr) {
245 public:
246  // Ports ...
247  sc_in<bool> clk, reset;
248  sc_in<sc_uint<32> > pc, ir;
249  sc_in<bool> exu_pop_priv_ir_stack_dreg; // trigger pushing the Privilege and Global Interrupt-Enable Stack
250 
251  sc_in<sc_uint<EX_ID_LENGTH> > ex_id_reg;
252  sc_in<bool> exception; // signal from ExU. Triggers saving of the exception state CSRs (mepc, mcause, ...)
253  sc_in<bool> irq_dreg; // Set if m3_ir_request is set during instruction decode (handle interrupt request)
254 
255  sc_out<bool> mtie_out; // mtie bit of mie register is set
256  sc_in<bool> mtip_in; // mtip bit of mip register
257  sc_in<bool> meip_in; // meip bit of mip register
258 
259  // misc (HLS reasons, should be optimized out while synthetization)
260  // these could be generics in VHDL, but current tools don't support that
261  sc_in<sc_uint<CFG_NUT_CPU_CORES_LD> > hartID;
262  sc_in<bool> inCePU;
263  sc_in<bool> cpu_enabled, linked;
264  sc_in<bool> csr_enable;
265  sc_in<sc_uint<5> > exu_cause;
266 
267  sc_in<bool> exu_dbg, exu_dbg_reg, exu_dbg_req, exu_dbg_enter_dreg;
268 
269  // Decode Registers
270  sc_out<bool> exu_delegate_dreg;
271  sc_in<bool> sret_dreg;
272 
273  sc_out<bool> exu_csr_exception; // Writes to read-only CSRs raise an exeption
274 
275  sc_out<bool>
276  exu_csr_mstatus_MIE, // Machine Interrupt Enable
277  exu_csr_mstatus_SIE,
278  exu_csr_mstatus_TSR, // Trap SRET
279  exu_csr_mstatus_TVM, // Trap Virtual Memory
280  exu_csr_mstatus_SUM,
281  exu_csr_dcsr_step,
282  exu_csr_dcsr_ebreakm;
283  sc_out<bool> exu_isHalted;
284 
285  sc_out<sc_uint<2> > exu_load_store_priv_mode;
286 
287  // Full registers
288  sc_out<sc_uint<32> >
289  exu_csr_mepc,
290  exu_csr_dpc,
291  exu_csr_mtvec,
292  exu_csr_mcause,
293  exu_csr_sepc,
294  exu_csr_stvec,
295  exu_csr_mideleg,
296  exu_csr_mip;
297 
298 
299  sc_out<bool> exu_ifu_paging_mode; // for instructions
300  sc_out<bool> exu_lsu_paging_mode; // for load-store OPs
301  sc_out<sc_uint<20> > exu_csr_satp_root_ppn;
302 
303  sc_out<sc_uint<CFG_NUT_CPU_CORES> > exu_m3_pnce;
304  sc_out<sc_uint<CFG_NUT_CPU_CORES> > exu_m3_pnlm;
305  sc_out<sc_uint<CFG_NUT_CPU_CORES> > exu_m3_pnxsel;
306  sc_in<sc_uint<2> > exu_m3_priv_mode;
307 
308  // EXU attention signals
309  sc_out<bool> exu_cache_flush;
310  sc_in<bool> exu_ack;
311 
312  // controller outputs...
313  sc_out<bool> exu_m3_icache_enable, exu_m3_dcache_enable;
314 
315  sc_in<sc_uint<32> > csr_tval; // Special signal for exception information input
316  sc_in<sc_uint<CFG_NUT_CPU_CORES> > m3_pnhaltreq;
317 
318  sc_in<sc_uint<3> > csr_function_reg;
319  sc_in<sc_uint<5> > csr_rs1_reg;
320  sc_in<sc_uint<12> > csr_adr_reg;
321  sc_in<sc_uint<32> > csr_op_a;
322  sc_out<sc_uint<32> > exu_csr_rdata;
323 
324  sc_out<sc_uint<2> > exu_priv_mode;
325 
326  // from CoPUs
327  sc_in<sc_uint<CFG_NUT_CPU_CORES> > m3_pnx;
328 
329 #if CFG_EXU_PERFCOUNT_ENABLE == 1
330  sc_in<bool> perf_inc;
331  sc_in<sc_uint<CFG_EXU_PERFCOUNTERS_LD> > perf_addr;
332 #endif
333 
334  // Functions
335  void Trace (sc_trace_file * tf, int levels = 1);
336 
337  // Processes...
338  void CSRHandleMethod ();
339  void CSRReadMethod ();
340  void CSRWriteMethod ();
341  void OutputMethod ();
342 
343  // Regular Methods
344  void setMstatus (sc_uint<32> wdata);
345  sc_uint<32> getMstatus ();
346  void setSstatus (sc_uint<32> wdata);
347  sc_uint<32> getSstatus ();
348 
349  SC_CTOR (MCsr) {
350  SC_METHOD (CSRHandleMethod);
351  sensitive << csr_enable << csr_function_reg << csr_op_a << csr_rs1_reg
352  << csr_rdata << csr_rd_exception << csr_adr_reg
353  << mtip_in;
354  SC_METHOD (CSRReadMethod);
355  sensitive << csr_adr_reg << csr_enable << csr_mepc << csr_mcause << csr_mtval
356  << csr_mtvec << csr_mscratch << csr_mstatus_MIE << csr_mstatus_MPIE
357  << exu_cause << m3_pnx << hartID << inCePU << cpu_enabled
358  << linked << csr_pncache << csr_mstatus_MPRV << csr_mstatus_MPP;
359  for (int i = 0; i < CFG_NUT_CPU_GROUPS + 1; i++)
360  sensitive << csr_pnce[i] << csr_pnece[i] << csr_pnlm[i] << csr_pnxsel[i] << csr_pnx[i];
361 #if CFG_NUT_CPU_GROUPS
362  sensitive << csr_pngrpsel;
363 #endif
364  SC_METHOD (CSRWriteMethod);
365  sensitive << clk.pos ();
366  SC_METHOD (OutputMethod);
367  sensitive << csr_exception << csr_rd_exception << exu_cache_flush_reg
368  << csr_mstatus_MIE << exu_csr_mstatus_SUM << csr_mstatus_TSR << csr_mstatus_TVM << csr_mstatus_SIE
369  << csr_mtvec << priv_mode_reg << csr_satp_root_ppn << csr_satp_mode
370  << csr_sepc << csr_stvec << csr_mideleg << delegate_dreg << csr_pncache
371  << csr_dcsr_step << csr_dcsr_ebreakm << csr_mcause << csr_rdata << csr_mepc << csr_dpc
372  << csr_mie_MTIE << csr_mstatus_MPP << csr_mstatus_MPRV;
373  for (int i = 0; i < CFG_NUT_CPU_GROUPS + 1; i++) {
374  sensitive << csr_pnce[i] << csr_pnece[i] << csr_pnlm[i] << csr_pnx[i] << csr_pnxsel[i];
375  }
376 
377 #if CFG_EXU_PERFCOUNT_ENABLE == 1
378  SC_METHOD (PerfcountMethod);
379  sensitive << clk.pos ();
380 #endif
381  }
382 
383 protected:
384  sc_signal<sc_uint<32> >
385  csr_wdata,
386  csr_rdata;
387 
388  sc_signal<bool>
389  csr_exception, // Writes to read-only CSRs raise an exeption
390  csr_rd_exception, // Reads to non-existent CSRs raise an exceptions
391  csr_write;
392 
393  sc_signal<sc_uint<2> > priv_mode_reg, next_priv_mode_reg;
394 
395  // Decode Registers
396  sc_signal<bool> delegate_dreg; // jump to stvec when set on exception
397  sc_signal<bool> exu_cache_flush_reg; // jump to stvec when set on exception
398 
399  // CSR registers
400  sc_signal<bool>
401  csr_dcsr_step,
402  csr_dcsr_ebreakm;
403  sc_signal<sc_uint<3> > csr_dcsr_cause;
404  sc_signal<sc_uint<2> > csr_dcsr_prv;
405 
406  sc_signal<bool>
407  csr_mip_MEIP, // Machine External Interrupt Pending
408  csr_mip_MTIP, // Machine Timer Interrupt Pending
409  csr_mie_MTIE, // Machine Timer Interrupt Enable
410  csr_mie_MEIE; // Machine External Interrupt Enable
411 
412  sc_signal<bool>
413  csr_mstatus_MPIE, // Machine Previous Interrupt Enable
414  csr_mstatus_MIE, // Machine Interrupt Enable
415  csr_mstatus_SIE, // Supervisor Interrupt Enable
416  csr_mstatus_SPIE, // Supervisor PreviousInterrupt Enable
417  csr_mstatus_SPP, // Supervisor Previous Privilege
418  csr_mstatus_SUM, // permit Supervisor User Memory access
419  csr_mstatus_MXR, // Make eXecutable Readable
420  csr_mstatus_TVM, // Trap Virtual Memory
421  csr_mstatus_TW, // Timeout Wait
422  csr_mstatus_TSR, // Trap SRET
423  csr_mstatus_SD, // State dirty
424  csr_mstatus_MPRV; // Modify Privilege
425  sc_signal<sc_uint<2> >
426  csr_mstatus_MPP, // Machine Previous Privilege
427  csr_mstatus_XS; // status of additional user-mode extensions
428 
429  sc_signal<bool> csr_satp_mode;
430  sc_signal<sc_uint<20> > csr_satp_root_ppn;
431 
432  sc_signal<sc_uint<32> >
433  csr_medeleg,
434  csr_mideleg,
435  csr_stvec,
436  csr_scause,
437  csr_stval,
438  csr_sepc,
439  csr_sscratch,
440  csr_mip,
441  csr_mie,
442  csr_mcause,
443  csr_dpc,
444  csr_dscratch0,
445  csr_mepc,
446  csr_mtval,
447  csr_mtvec,
448  csr_mscratch;
449 
450  // If there are more than 32 CPUs only full 32 bit CSRs are supported/possible at the moment
451  sc_signal<sc_uint<MIN (XLEN, CFG_NUT_CPU_CORES)> >
452  csr_pnce[CFG_NUT_CPU_GROUPS + 1],
453  csr_pnece[CFG_NUT_CPU_GROUPS + 1],
454  csr_pnlm[CFG_NUT_CPU_GROUPS + 1],
455  csr_pnx[CFG_NUT_CPU_GROUPS + 1],
456  csr_pnxsel[CFG_NUT_CPU_GROUPS + 1];
457 
458 #if CFG_NUT_CPU_GROUPS > 0
459  // With more than 32 CPUs create a csr_pngrpsel signal
460  sc_signal<sc_uint<CFG_NUT_CPU_GROUPS> > csr_pngrpsel;
461 #else
462  // With less than 32 CPUs don't create a csr_pngrpsel signal, just static const variable
463  static const bool csr_pngrpsel = 0x0;
464 #endif
465  sc_signal<sc_uint<2> > csr_pncache;
466 
467 #if CFG_EXU_PERFCOUNT_ENABLE == 1
468  // Perfcount Method ...
469  void PerfcountMethod ();
470  // Perfcount signals ...
471  sc_signal<sc_uint<64> > csr_mcycle;
472  sc_signal<sc_uint<CFG_EXU_PERFCOUNTER_BITS> > csr_mhpmcounter[CFG_EXU_PERFCOUNTERS];
473 #endif
474 };
Helpers, Makros and performance measuring Classes used in most ParaNut files.
ECSR
Definition: csr.h:64
@ uhpmcounter17h
Definition: csr.h:193
@ uhpmcounter31
Definition: csr.h:175
@ ucause
Definition: csr.h:139
@ uhpmcounter8
Definition: csr.h:152
@ mip
Definition: csr.h:84
@ mimpid
Definition: csr.h:68
@ uhpmcounter22
Definition: csr.h:166
@ uip
Definition: csr.h:141
@ uhpmcounter5h
Definition: csr.h:181
@ uhpmcounter11
Definition: csr.h:155
@ uhpmcounter24
Definition: csr.h:168
@ utval
Definition: csr.h:140
@ uhpmcounter29h
Definition: csr.h:205
@ utime
Definition: csr.h:145
@ sedeleg
Definition: csr.h:115
@ sideleg
Definition: csr.h:116
@ pngrpsel
Definition: csr.h:219
@ uhpmcounter28h
Definition: csr.h:204
@ uhpmcounter5
Definition: csr.h:149
@ pnmemsize
Definition: csr.h:230
@ uhpmcounter6h
Definition: csr.h:182
@ uhpmcounter6
Definition: csr.h:150
@ pnclockinfo
Definition: csr.h:229
@ uhpmcounter8h
Definition: csr.h:184
@ uhpmcounter20h
Definition: csr.h:196
@ sie
Definition: csr.h:117
@ mstatus
Definition: csr.h:72
@ mcycle
Definition: csr.h:87
@ pnlm
Definition: csr.h:221
@ uhpmcounter24h
Definition: csr.h:200
@ pncachesets
Definition: csr.h:228
@ pnepc
Definition: csr.h:239
@ mhpmcounter4
Definition: csr.h:90
@ dpc
Definition: csr.h:211
@ satp
Definition: csr.h:129
@ mhpmevent3
Definition: csr.h:109
@ stval
Definition: csr.h:125
@ mhpmcounter4h
Definition: csr.h:100
@ uhpmcounter25h
Definition: csr.h:201
@ mhpmcounter6h
Definition: csr.h:102
@ ustatus
Definition: csr.h:132
@ mhpmcounter7h
Definition: csr.h:103
@ mhpmcounter8
Definition: csr.h:94
@ sstatus
Definition: csr.h:114
@ uhpmcounter18h
Definition: csr.h:194
@ uhpmcounter27h
Definition: csr.h:203
@ pncpus
Definition: csr.h:235
@ uhpmcounter12h
Definition: csr.h:188
@ uhpmcounter25
Definition: csr.h:169
@ uhpmcounter9
Definition: csr.h:153
@ uhpmcounter21h
Definition: csr.h:197
@ mcycleh
Definition: csr.h:97
@ mhpmcounter7
Definition: csr.h:93
@ mhpmcounter8h
Definition: csr.h:104
@ uhpmcounter7h
Definition: csr.h:183
@ uhpmcounter13
Definition: csr.h:157
@ mtval
Definition: csr.h:83
@ pnx
Definition: csr.h:226
@ dscratch0
Definition: csr.h:212
@ mhpmevent31
Definition: csr.h:111
@ uhpmcounter12
Definition: csr.h:156
@ pnxsel
Definition: csr.h:222
@ uhpmcounter30
Definition: csr.h:174
@ uinstret
Definition: csr.h:146
@ pncache
Definition: csr.h:216
@ uhpmcounter19
Definition: csr.h:163
@ uhpmcounter22h
Definition: csr.h:198
@ mhpmcounter31h
Definition: csr.h:106
@ uhpmcounter31h
Definition: csr.h:207
@ minstreth
Definition: csr.h:98
@ scounteren
Definition: csr.h:119
@ stvec
Definition: csr.h:118
@ uhpmcounter3
Definition: csr.h:147
@ uhpmcounter17
Definition: csr.h:161
@ uhpmcounter18
Definition: csr.h:162
@ misa
Definition: csr.h:73
@ uhpmcounter27
Definition: csr.h:171
@ uhpmcounter15
Definition: csr.h:159
@ utvec
Definition: csr.h:134
@ uie
Definition: csr.h:133
@ pncoreid
Definition: csr.h:236
@ mtvec
Definition: csr.h:77
@ uhpmcounter20
Definition: csr.h:164
@ mhpmcounter3h
Definition: csr.h:99
@ uhpmcounter26h
Definition: csr.h:202
@ mhpmcounter5
Definition: csr.h:91
@ uhpmcounter4h
Definition: csr.h:180
@ mvendorid
Definition: csr.h:66
@ pncause
Definition: csr.h:240
@ scause
Definition: csr.h:124
@ pntimebase
Definition: csr.h:232
@ ucycleh
Definition: csr.h:176
@ uhpmcounter3h
Definition: csr.h:179
@ uhpmcounter10
Definition: csr.h:154
@ pncacheinfo
Definition: csr.h:227
@ uhpmcounter16
Definition: csr.h:160
@ uhpmcounter13h
Definition: csr.h:189
@ medeleg
Definition: csr.h:74
@ minstret
Definition: csr.h:88
@ mhpmcounter3
Definition: csr.h:89
@ uhpmcounter29
Definition: csr.h:173
@ uhpmcounter30h
Definition: csr.h:206
@ tselect
Definition: csr.h:213
@ marchid
Definition: csr.h:67
@ mepc
Definition: csr.h:81
@ uhpmcounter7
Definition: csr.h:151
@ uhpmcounter21
Definition: csr.h:165
@ mhpmcounter6
Definition: csr.h:92
@ mscratch
Definition: csr.h:80
@ uhpmcounter15h
Definition: csr.h:191
@ mhpmcounter31
Definition: csr.h:96
@ uhpmcounter14h
Definition: csr.h:190
@ dcsr
Definition: csr.h:210
@ ucycle
Definition: csr.h:144
@ uscratch
Definition: csr.h:137
@ uinstreth
Definition: csr.h:178
@ uepc
Definition: csr.h:138
@ uhpmcounter9h
Definition: csr.h:185
@ uhpmcounter4
Definition: csr.h:148
@ mhpmcounter5h
Definition: csr.h:101
@ sepc
Definition: csr.h:123
@ sip
Definition: csr.h:126
@ uhpmcounter23h
Definition: csr.h:199
@ uhpmcounter26
Definition: csr.h:170
@ uhpmcounter28
Definition: csr.h:172
@ uhpmcounter16h
Definition: csr.h:192
@ uhpmcounter11h
Definition: csr.h:187
@ uhpmcounter10h
Definition: csr.h:186
@ uhpmcounter14
Definition: csr.h:158
@ uhpmcounter23
Definition: csr.h:167
@ mideleg
Definition: csr.h:75
@ mie
Definition: csr.h:76
@ mcause
Definition: csr.h:82
@ utimeh
Definition: csr.h:177
@ pnece
Definition: csr.h:231
@ uhpmcounter19h
Definition: csr.h:195
@ sscratch
Definition: csr.h:122
@ pnm2cp
Definition: csr.h:225
@ pnce
Definition: csr.h:220
@ mhartid
Definition: csr.h:69
ECSRFunc
Definition: csr.h:57
@ CSRRC
Definition: csr.h:60
@ CSRRS
Definition: csr.h:59
@ CSRRW
Definition: csr.h:58
sc_signal< bool > reset
Definition: dm_tb.cpp:54
sc_signal< bool > clk
Definition: dm_tb.cpp:54
#define CFG_EXU_PERFCOUNTERS
Performance counter number of registers (derived).
Definition: paranut-config.h:169
#define CFG_NUT_CPU_CORES
Number of cores overall (derived).
Definition: paranut-config.h:98
#define CFG_NUT_CPU_GROUPS
Number of cpu groups (derived).
Definition: paranut-config.h:100
#define XLEN
Number of instruction/register Bits.
Definition: base.h:164
#define MIN(A, B)
Minimum of A and B.
Definition: base.h:152
Configuration Makros used in most ParaNut files.
The MPeripheral class containing the interface for Wishbone slave peripherals.
sc_trace_file * tf
Definition: tlb_tb.cpp:94