ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
Macros | Functions | Variables
memu_tb.cpp File Reference
#include "paranut-sim.h"
#include "memory.h"
#include <systemc.h>
#include <stdio.h>
Include dependency graph for memu_tb.cpp:

Macros

#define WORDS_BIGENDIAN   0
 
#define BSEL(bsel)
 
#define CLK_PERIOD   10.0
 

Functions

void RunCycle (int n=1)
 
void ClearReadPort (int p)
 
void ClearWritePort (int p)
 
void WriteInit (int p, TWord adr, TWord data, sc_uint< 4 > bsel=0xf)
 
void WriteInitSpecial (int p, TWord adr, bool writeback, bool invalidate)
 
bool WriteTryComplete (int p)
 
void WriteComplete (int p)
 
void Write (int p, TWord adr, TWord data, sc_uint< 4 > bsel=0xf)
 
void WriteSpecial (int p, TWord adr, bool writeback, bool invalidate)
 
void RunPartwordReadWrite (int port, TByte id, TWord base, TWord stride=4, int count=1)
 
void RunParallelReadWrite (TWord id, TWord base0, TWord stride0, TWord base1, TWord stride1)
 
void RunRandomReadWrite (TWord adrrange, int iterations)
 
void RunPerformanceTest (TWord adr, TWord id)
 
void RunSpecial (int port, TWord adr, TWord id)
 
void RunLlSc (TWord adr, TWord id)
 
void RunTest ()
 
int sc_main (int argc, char *argv[])
 

Variables

sc_signal< bool > clk
 
sc_signal< bool > reset
 
sc_signal< bool > wb_cyc
 
sc_signal< bool > wb_stb
 
sc_signal< bool > wb_we
 
sc_signal< bool > wb_ack
 
sc_signal< bool > wb_err
 
sc_signal< bool > wb_rty
 
sc_signal< sc_uint< 3 > > wb_cti
 
sc_signal< sc_uint< 2 > > wb_bte
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > wb_sel
 
sc_signal< sc_uint< 32 > > wb_adr
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_w
 
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_r
 
sc_signal< bool > dbg_ack
 
sc_signal< bool > dbg_err
 
sc_signal< bool > dbg_rty
 
sc_signal< TWorddbg_dat
 
sc_signal< bool > rp_rd [CFG_MEMU_RPORTS]
 
sc_signal< bool > rp_direct [CFG_MEMU_RPORTS]
 
sc_signal< bool > rp_ack [CFG_MEMU_RPORTS]
 
sc_signal< sc_uint< 4 > > rp_bsel [CFG_MEMU_RPORTS]
 
sc_signal< TWordrp_adr [CFG_MEMU_RPORTS]
 
sc_signal< TWordrp_data [CFG_MEMU_RPORTS]
 
sc_signal< bool > wp_wr [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_direct [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 4 > > wp_bsel [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_ack [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_lres_scond [CFG_MEMU_WPORTS]
 
sc_signal< bool > wp_scond_ok [CFG_MEMU_WPORTS]
 
sc_signal< sc_uint< 3 > > wp_cache_op [CFG_MEMU_WPORTS]
 
sc_signal< TWordwp_adr [CFG_MEMU_WPORTS]
 
sc_signal< TWordwp_data [CFG_MEMU_WPORTS]
 
int cfg_help = 0
 

Macro Definition Documentation

◆ BSEL

#define BSEL (   bsel)
Value:
(((TByte)(bsel << 3) & 0x8) |\
((TByte)(bsel << 1) & 0x4) |\
((TByte)(bsel >> 1) & 0x2) |\
((TByte)(bsel >> 3) & 0x1))
unsigned char TByte
Byte type (8 Bit).
Definition: base.h:143

◆ CLK_PERIOD

#define CLK_PERIOD   10.0

◆ WORDS_BIGENDIAN

#define WORDS_BIGENDIAN   0

Function Documentation

◆ ClearReadPort()

void ClearReadPort ( int  p)

◆ ClearWritePort()

void ClearWritePort ( int  p)

◆ RunCycle()

void RunCycle ( int  n = 1)

◆ RunLlSc()

void RunLlSc ( TWord  adr,
TWord  id 
)

◆ RunParallelReadWrite()

void RunParallelReadWrite ( TWord  id,
TWord  base0,
TWord  stride0,
TWord  base1,
TWord  stride1 
)

◆ RunPartwordReadWrite()

void RunPartwordReadWrite ( int  port,
TByte  id,
TWord  base,
TWord  stride = 4,
int  count = 1 
)

◆ RunPerformanceTest()

void RunPerformanceTest ( TWord  adr,
TWord  id 
)

◆ RunRandomReadWrite()

void RunRandomReadWrite ( TWord  adrrange,
int  iterations 
)

◆ RunSpecial()

void RunSpecial ( int  port,
TWord  adr,
TWord  id 
)

◆ RunTest()

void RunTest ( )

◆ sc_main()

int sc_main ( int  argc,
char *  argv[] 
)

◆ Write()

void Write ( int  p,
TWord  adr,
TWord  data,
sc_uint< 4 >  bsel = 0xf 
)

◆ WriteComplete()

void WriteComplete ( int  p)

◆ WriteInit()

void WriteInit ( int  p,
TWord  adr,
TWord  data,
sc_uint< 4 >  bsel = 0xf 
)

◆ WriteInitSpecial()

void WriteInitSpecial ( int  p,
TWord  adr,
bool  writeback,
bool  invalidate 
)

◆ WriteSpecial()

void WriteSpecial ( int  p,
TWord  adr,
bool  writeback,
bool  invalidate 
)

◆ WriteTryComplete()

bool WriteTryComplete ( int  p)

Variable Documentation

◆ cfg_help

int cfg_help = 0

◆ clk

sc_signal<bool> clk

◆ dbg_ack

sc_signal<bool> dbg_ack

◆ dbg_dat

sc_signal<TWord> dbg_dat

◆ dbg_err

sc_signal<bool> dbg_err

◆ dbg_rty

sc_signal<bool> dbg_rty

◆ reset

sc_signal<bool> reset

◆ rp_ack

sc_signal<bool> rp_ack[CFG_MEMU_RPORTS]

◆ rp_adr

sc_signal<TWord> rp_adr[CFG_MEMU_RPORTS]

◆ rp_bsel

sc_signal<sc_uint<4> > rp_bsel[CFG_MEMU_RPORTS]

◆ rp_data

sc_signal<TWord> rp_data[CFG_MEMU_RPORTS]

◆ rp_direct

sc_signal<bool> rp_direct[CFG_MEMU_RPORTS]

◆ rp_rd

sc_signal<bool> rp_rd[CFG_MEMU_RPORTS]

◆ wb_ack

sc_signal<bool> wb_ack

◆ wb_adr

sc_signal<sc_uint<32> > wb_adr

◆ wb_bte

sc_signal<sc_uint<2> > wb_bte

◆ wb_cti

sc_signal<sc_uint<3> > wb_cti

◆ wb_cyc

sc_signal<bool> wb_cyc

◆ wb_dat_r

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat_r

◆ wb_dat_w

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat_w

◆ wb_err

sc_signal<bool> wb_err

◆ wb_rty

sc_signal<bool> wb_rty

◆ wb_sel

sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > wb_sel

◆ wb_stb

sc_signal<bool> wb_stb

◆ wb_we

sc_signal<bool> wb_we

◆ wp_ack

sc_signal<bool> wp_ack[CFG_MEMU_WPORTS]

◆ wp_adr

sc_signal<TWord> wp_adr[CFG_MEMU_WPORTS]

◆ wp_bsel

sc_signal<sc_uint<4> > wp_bsel[CFG_MEMU_WPORTS]

◆ wp_cache_op

sc_signal<sc_uint<3> > wp_cache_op[CFG_MEMU_WPORTS]

◆ wp_data

sc_signal<TWord> wp_data[CFG_MEMU_WPORTS]

◆ wp_direct

sc_signal<bool> wp_direct[CFG_MEMU_WPORTS]

◆ wp_lres_scond

sc_signal<bool> wp_lres_scond[CFG_MEMU_WPORTS]

◆ wp_scond_ok

sc_signal<bool> wp_scond_ok[CFG_MEMU_WPORTS]

◆ wp_wr

sc_signal<bool> wp_wr[CFG_MEMU_WPORTS]