ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
interconnect.h
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1 /*************************************************************************
2 
3  This file is part of the ParaNut project.
4 
5  Copyright (C) 2020 Alexander Bahle <alexander.bahle@hs-augsburg.de>
6  Hochschule Augsburg, University of Applied Sciences
7 
8  Description:
9  This is a SystemC model of a Wishbone interconnect exclusively for
10  simulation purpose.
11  Features 1 master input and CFG_NUT_SIM_MAX_PERIPHERY slave outputs (see config)
12 
13  Redistribution and use in source and binary forms, with or without modification,
14  are permitted provided that the following conditions are met:
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35 
36 
37 #ifndef _INTERCONNECT_H
38 #define _INTERCONNECT_H
39 
40 
41 #include "paranut-peripheral.h"
42 
43 struct SInterPeriph {
45  size_t size;
46 };
47 
48 // **************** MInterconnect *************
49 class MInterconnect : ::sc_core::sc_module {
50 public:
51  // Ports (WISHBONE slave)...
52  sc_in_clk clk_i; // clock input
53  sc_in<bool> rst_i; // reset
54 
55  sc_in<bool> stb_i; // strobe input
56  sc_in<bool> cyc_i; // cycle valid input
57  sc_in<bool> we_i; // indicates write transfer
58  sc_out<sc_uint<3> > cti_i; // cycle type identifier
59  sc_out<sc_uint<2> > bte_i; // burst type extension
60  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > sel_i; // byte select inputs
61  sc_out<bool> ack_o; // normal termination
62  sc_out<bool> err_o; // termination w/ error
63  sc_out<bool> rty_o; // termination w/ retry
64 
65  sc_in<sc_uint<32> > adr_i; // address bus inputs
66  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dat_i; // input data bus
67  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dat_o; // output data bus
68 
69  // Constructor...
70  SC_HAS_PROCESS (MInterconnect);
71  MInterconnect (sc_module_name name)
72  : sc_module (name) {
73  SC_METHOD (InterconnectMethod);
74  sensitive << stb_i << cyc_i << we_i << sel_i << cti_i << bte_i;
75  sensitive << adr_i << dat_i;
76  for (int n = 0; n < CFG_NUT_SIM_MAX_PERIPHERY; n++)
77  sensitive << ack[n] << rty[n] << err[n] << dat[n];
78 
79  num_peri_ = 0;
80  }
81 
82  // Functions...
83  void Trace (sc_trace_file * tf, int level = 1);
84  void AddSlave(TWord start_adr, size_t size, MPeripheral *slave);
85  void AddSlave(TWord start_adr, size_t size,
86  sc_in_clk *wb_clk_i, sc_in<bool> *wb_rst_i, sc_in<bool> *wb_stb_i,
87  sc_in<bool> *wb_cyc_i, sc_in<bool> *wb_we_i, sc_in<sc_uint<3> > *wb_cti_i,
88  sc_in<sc_uint<2> > *wb_bte_i, sc_in<sc_uint<WB_PORT_SIZE/8> > *wb_sel_i,
89  sc_out<bool> *wb_ack_o, sc_out<bool> *wb_err_o, sc_out<bool> *wb_rty_o,
90  sc_in<sc_uint<32> > *wb_adr_i, sc_in<sc_uint<WB_PORT_SIZE> > *wb_dat_i,
91  sc_out<sc_uint<WB_PORT_SIZE> > *wb_dat_o);
92 
93  // Processes...
94  void InterconnectMethod ();
95 
96 private:
97  int num_peri_;
99 
100  // Internal signals...
101  sc_signal<bool> stb[CFG_NUT_SIM_MAX_PERIPHERY],
105  sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dat[CFG_NUT_SIM_MAX_PERIPHERY];
106 
107 
108 };
109 
110 #endif // _INTERCONNECT_H
Definition: interconnect.h:49
sc_in< sc_uint< 32 > > adr_i
Definition: interconnect.h:65
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_o
Definition: interconnect.h:67
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > sel_i
Definition: interconnect.h:60
sc_in< bool > rst_i
Definition: interconnect.h:53
void Trace(sc_trace_file *tf, int level=1)
Definition: interconnect.cpp:40
void InterconnectMethod()
Definition: interconnect.cpp:140
void AddSlave(TWord start_adr, size_t size, MPeripheral *slave)
Definition: interconnect.cpp:128
sc_in< bool > we_i
Definition: interconnect.h:57
sc_in_clk clk_i
Definition: interconnect.h:52
sc_out< bool > ack_o
Definition: interconnect.h:61
sc_in< bool > stb_i
Definition: interconnect.h:55
sc_out< bool > rty_o
Definition: interconnect.h:63
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_i
Definition: interconnect.h:66
sc_out< bool > err_o
Definition: interconnect.h:62
sc_out< sc_uint< 2 > > bte_i
Definition: interconnect.h:59
sc_out< sc_uint< 3 > > cti_i
Definition: interconnect.h:58
MInterconnect(sc_module_name name)
Definition: interconnect.h:71
sc_in< bool > cyc_i
Definition: interconnect.h:56
Class containing the interface for Wishbone slave peripherals.
Definition: paranut-peripheral.h:75
#define CFG_MEMU_BUSIF_WIDTH
Busif Data Width.
Definition: paranut-config.h:228
#define CFG_NUT_SIM_MAX_PERIPHERY
Simulation maximum peripherals number.
Definition: paranut-config.h:78
unsigned TWord
Word type (32 Bit).
Definition: base.h:147
The MPeripheral class containing the interface for Wishbone slave peripherals.
Definition: interconnect.h:43
size_t size
Definition: interconnect.h:45
TWord adr
Definition: interconnect.h:44
sc_trace_file * tf
Definition: tlb_tb.cpp:94