ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
memu.h
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1 /*************************************************************************
2 
3  This file is part of the ParaNut project.
4 
5  Copyright (C) 2010-2022 Alexander Bahle <alexander.bahle@hs-augsburg.de>
6  Gundolf Kiefer <gundolf.kiefer@hs-augsburg.de>
7  Christian H. Meyer <christian.meyer@hs-augsburg.de>
8  Hochschule Augsburg, University of Applied Sciences
9 
10  Description:
11  This is the memory unit (MEMU) of the ParaNut.
12  The MEMU interfaces with the main memory bus over a wishbone interface
13  and with the ParaNut CPUs over an arbitrary number of read and write
14  ports. The MEMU contains the (shared) cache and is optimize to handle
15  parallel memory accesses from different ports efficiently.
16  Also, the support for synchronization primitives is due to the MEMU.
17 
18  The MEMU (class 'MMemu') contains the following sub-modules:
19  - 1 tag RAM ('MTagRAM) for storing and supplying cache tag information
20  - CFG_MEMU_CACHE_BANKS cache memory banks ('MBankRam') for storing cached data
21  - 1 bus interface ('MBusIF') for the Wishbone interconnection
22  - RPORTS read ports ('MReadPort')
23  - WPORTS write ports ('MWritePort')
24  - 1 arbiter ('MArbiter') for controlling the access to the caches' tag
25  and bank data
26 
27  Redistribution and use in source and binary forms, with or without modification,
28  are permitted provided that the following conditions are met:
29 
30  1. Redistributions of source code must retain the above copyright notice, this
31  list of conditions and the following disclaimer.
32 
33  2. Redistributions in binary form must reproduce the above copyright notice,
34  this list of conditions and the following disclaimer in the documentation and/or
35  other materials provided with the distribution.
36 
37  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
38  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
39  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
40  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
41  ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
44  ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
46  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 
48  *************************************************************************/
49 
50 
51 #ifndef _MEMU_
52 #define _MEMU_
53 
54 #include "base.h"
55 #include "paranut-config.h"
56 
57 #include <systemc.h>
58 #include "ptw.h"
59 #include "tlb.h"
60 
61 #define MASTER_NO 2
62 
63 /*
64  To-Do (TBD)
65  -----
66 
67  - (EXAMINE: priority: RD/RI/WD per core, not global? -> starvation may occur if global)
68  - (optimize BusIf: reset 'busy' before WB write-back -> does not really help)
69 */
70 
71 // MArbiter Selector input/output type...
72 template<int DWIDTH = 1, int SEL_MAX = 1>
73 struct SSelectorIO {
74  sc_uint<DWIDTH> dat;
75  sc_uint<NUM_BITS(SEL_MAX)> sel;
76  bool sel_valid;
77 
78  SSelectorIO( sc_uint<DWIDTH> _dat = 0, sc_uint<NUM_BITS(SEL_MAX)> _sel = 0, bool _sel_valid = 0): dat(_dat), sel(_sel), sel_valid(_sel_valid) { }
79 
80  // Necessary operators for using this structure as signals...
81  // Compare (necessary for signal updates)...
82  bool operator == (const SSelectorIO &t) {
83  return (dat == t.dat) && (sel == t.sel) && (sel_valid == t.sel_valid);
84  }
85  // Display...
86  friend ostream& operator<< (ostream &o, const SSelectorIO &t ) {
87  o << "{" << t.dat << "," << t.sel << "," << t.sel_valid << "}" ;
88  return o;
89  }
90  // Tracing...
91  friend void sc_trace( sc_trace_file *tf, const SSelectorIO &t, const std::string &name ) {
92  PN_TRACE_R (tf, t, dat, name);
93  PN_TRACE_R (tf, t, sel, name);
94  PN_TRACE_R (tf, t, sel_valid, name);
95  }
96  };
97 
98 template<int DWIDTH = 1, int SEL_MAX = 1>
99 struct MSelectorPass: sc_module {
100 public:
101  // Ports ...
102  sc_in<SSelectorIO<DWIDTH, SEL_MAX> > f_in;
103  sc_out<SSelectorIO<DWIDTH, SEL_MAX> > out;
104 
105  void CombMethod() {
106  out = f_in.read ();
107  }
108 
109  SC_HAS_PROCESS(MSelectorPass); // Necessary when not using SC_MODULE macro
110  MSelectorPass (const sc_module_name &name) : sc_module (name),
111  f_in ("f_in"), out ("out")
112  {
113  SC_METHOD(CombMethod);
114  sensitive << f_in ;
115  }
116 
117  // Functions...
118  void Trace (sc_trace_file *tf, int level) {
119  PN_TRACE (tf, f_in);
120  PN_TRACE (tf, out);
121  }
122 };
123 
124 template<int DWIDTH = 1, int SEL_MAX = 1>
125 struct MSelector: sc_module {
126 public:
127  // Ports ...
128  sc_in<bool> clk, reset;
129  sc_in<SSelectorIO<DWIDTH, SEL_MAX> > f_in, s_in;
130  sc_out<SSelectorIO<DWIDTH, SEL_MAX> > out;
131  sc_in<sc_uint<MAX(1, CFG_NUT_CPU_CORES_LD)> > prio;
132 
134  if (reset == 1) {
135  SSelectorIO<DWIDTH, SEL_MAX> reg; // Default constructor is (0, 0, 0)
136  s_in_reg = reg;
137  } else
138  s_in_reg = next_s_in_reg.read ();
139  }
140 
141  void CombMethod() {
142  SSelectorIO<DWIDTH, SEL_MAX> reg, f_in_var, s_in_var, out_var;
143  bool slow_sel_valid;
144 
145  // Read inputs...
146  f_in_var = f_in.read ();
147  s_in_var = s_in.read ();
148 
149  // Set defaults...
150  reg = s_in_reg.read ();
151  slow_sel_valid = (reg.sel_valid & s_in_var.sel_valid) && (reg.sel == s_in_var.sel);
152 
153  if (prio.read () <= FAST_INDEX)
154  // Fast input has priority...
155  if (f_in_var.sel_valid)
156  out_var = f_in_var;
157  else
158  out_var = reg;
159  else
160  // Slow input has priority...
161  if (slow_sel_valid)
162  out_var = reg;
163  else
164  out_var = f_in_var;
165 
166  // Set output valid...
167  out_var.sel_valid = f_in_var.sel_valid | slow_sel_valid;
168 
169  // Write results...
170  next_s_in_reg = s_in_var;
171  out = out_var;
172  }
173 
174  SC_HAS_PROCESS(MSelector); // Necessary when not using SC_MODULE macro
175  MSelector (const sc_module_name &name, sc_uint<32> FAST_INDEX = 0) : sc_module(name),
176  clk ("clk"), reset ("reset"), f_in ("f_in"), s_in ("s_in"), out ("out"), prio ("prio"),
177  FAST_INDEX(FAST_INDEX)
178  {
179  SC_METHOD(TransitionMethod);
180  sensitive << clk.pos();
181  SC_METHOD(CombMethod);
182  sensitive << f_in << s_in << s_in_reg << prio;
183  }
184 
185  // Functions...
186  void Trace (sc_trace_file *tf, int level) {
187  PN_TRACE (tf, clk);
188  PN_TRACE (tf, reset);
189  PN_TRACE (tf, f_in);
190  PN_TRACE (tf, s_in);
191  PN_TRACE (tf, out);
192  PN_TRACE (tf, prio);
193  PN_TRACE (tf, s_in_reg);
194  }
195  private:
196  const sc_uint<32> FAST_INDEX;
197 
198  // Registers...
199  sc_signal<SSelectorIO<DWIDTH, SEL_MAX> > s_in_reg;
200 
201  // Signals...
202  sc_signal<SSelectorIO<DWIDTH, SEL_MAX> > next_s_in_reg;
203 };
204 
205 
206 
207 struct SCacheTag {
208  bool valid, dirty;
209  bool ac_r, ac_w, ac_x, ac_u; // Paging flags
211  sc_uint<CFG_MEMU_CACHE_WAYS_LD> way;
212 
213  // Necessary operators for using this structure as signals...
214  // Compare (necessary for signal updates)...
215  bool operator== (const SCacheTag &t) const;
216  // Display...
217  friend ostream &operator<< (ostream &os, const SCacheTag &t);
218  // Tracing...
219  friend void sc_trace (sc_trace_file *tf, const SCacheTag &t, const std::string &name);
220 };
221 
222 
223 // Examples:
224 // a) 4 banks/16 bytes per line, 512 lines
225 // -> size = 16 * 512 = 8 KB
226 // -> 32-9-2-2 = 19 adress bits / 21 tag bits -> tag memory must be 32 bits wide
227 //
228 // b) 8 banks/32 bytes per line, 8192 lines
229 // -> size = 32 * 8192 = 256 KB
230 // -> 32-13-3-2 = 14 adress bits / 16 tag bits -> tag memory may be 16 bits wide
231 
232 
233 // **************** MTagRam ******************
234 
235 #define TR_PORTS CFG_NUT_CPU_CORES // see comment to 'MArbiter'
236 
237 // Tag layout in memory
238 // | Valid bit | Dirty bit | Read (Paging) | Write (Paging) | Execute (Paging) | User (Paging) | Accessed (Paging) | Dirty (Paging) | Tag address |
239 struct STag {
240  bool valid, dirty;
241  bool ac_r, ac_w, ac_x, ac_u; // Paging flags
243 };
244 
245 // Tag entry layout in memory
246 // | Tags (way(0)..way(n-1)) | LRU info |
247 struct STagEntry {
249  sc_uint<6> use; // only used with LRU replacement (Note: saved in its own block ram in hardware)
250 };
251 
252 /*
253  // Necessary operators for using this structure as signals...
254  bool operator== (const STagEntry& t) const;
255  STagEntry& operator= (const STagEntry& t);
256 };
257 
258 ostream& operator<< (ostream& os, const STagEntry& t);
259 void sc_trace (sc_trace_file *tf, const STagEntry& t, const std::string& name);
260 */
261 
262 
263 class MTagRam : ::sc_core::sc_module {
264 public:
265  // Ports ...
266  sc_in<bool> clk, reset;
267  sc_out<bool> ready; // indicates that reset has been completed
268 
269  sc_in<bool> rd[TR_PORTS],
272 
273  sc_in<sc_uint<32> > adr[TR_PORTS]; // complete adress (lower CFG_MEMU_CACHE_BANKS_LD + 2 bits can be omitted)
274  sc_in<sc_uint<32> > wadr[TR_PORTS]; // complete write adress (lower CFG_MEMU_CACHE_BANKS_LD + 2 bits can be omitted)
275  sc_in<SCacheTag> tag_in[TR_PORTS];
276  // TBD: only the BusIf needs this port, write ports only set the dirty bit -> a 'wr_dirty' signal is sufficient
277  sc_out<SCacheTag> tag_out[TR_PORTS];
278 
279  // Constructor...
280  SC_HAS_PROCESS (MTagRam);
281  MTagRam (sc_module_name name)
282  : sc_module (name) {
283  SC_THREAD (MainThread);
284  sensitive << clk.pos ();
285  reset_signal_is (reset, true);
286  }
287 
288  // Functions...
289  void Trace (sc_trace_file * tf, int level = 1);
290 
291  // Processes...
292  void MainThread ();
293 
294 protected:
296 
297  // Registers...
298  sc_signal<bool> write_tag;
299  sc_signal<sc_uint<CFG_MEMU_CACHE_WAYS_LD> > wtag_way;
300  sc_signal<sc_uint<32> > wtag_iadr;
301  sc_signal<sc_uint<32> > wtag_port;
302  // for LRU replacement...
303  sc_signal<sc_uint<6>> use_reg[TR_PORTS+1], use_iadr_reg[TR_PORTS+1]; // One for each reader + one for all writer
304  sc_signal<bool> use_wr_reg[TR_PORTS+1]; // One for each reader + one for all writer
305  // for random replacement...
306  sc_signal<sc_uint<8> > counter;
307 };
308 
309 
310 // **************** MBankRam ********************
311 
312 class MBankRam : ::sc_core::sc_module {
313 public:
314  // Ports ...
315  sc_in<bool> clk;
316 
318 
319  sc_in<sc_uint<4> > wen[CFG_MEMU_BANK_RAM_PORTS]; // byte write enable bits
320 
321  sc_in<sc_uint<32> > wiadr[CFG_MEMU_BANK_RAM_PORTS]; // line adress (way & index bits of adress)
322  sc_in<sc_uint<32> > wdata[CFG_MEMU_BANK_RAM_PORTS];
323  sc_out<sc_uint<32> > rdata[CFG_MEMU_BANK_RAM_PORTS];
324 
325  // Constructor...
326  SC_HAS_PROCESS (MBankRam);
327  MBankRam (sc_module_name name)
328  : sc_module (name) { SC_CTHREAD (MainThread, clk.pos ()); }
329 
330  // Functions...
331  void Trace (sc_trace_file * tf, int level = 1);
332 
333  // Processes...
334  void MainThread ();
335 
336 protected:
338 };
339 
340 
341 // **************** MBusController **********************
342 
343 SC_MODULE(MBusController) {
344 public:
345  // Bus interface (Wishbone)...
346  sc_out<bool> wb_cyc_o; // cycle valid output
347  sc_out<bool> wb_stb_o; // strobe output
348  sc_out<bool> wb_we_o; // indicates write transfer
349  sc_out<sc_uint<3> > wb_cti_o; // cycle type identifier
350  sc_out<sc_uint<2> > wb_bte_o; // burst type extension
351  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > wb_sel_o; // byte select outputs
352  sc_out<sc_uint<32> > wb_adr_o; // address bus outputs
353  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat_o; // output data bus
354 
355  sc_in<bool> master_cyc[MASTER_NO];
356  sc_in<bool> master_stb[MASTER_NO];
357  sc_in<bool> master_we[MASTER_NO];
358  sc_in<sc_uint<3> > master_cti[MASTER_NO];
359  sc_in<sc_uint<2> > master_bte[MASTER_NO];
360  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > master_sel[MASTER_NO];
361  sc_in<sc_uint<32> > master_adr[MASTER_NO];
362  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > master_dat[MASTER_NO];
363 
364  // Control inputs...
365  sc_in<bool> switch_master;
366 
367 
368  // Constructor...
369  SC_CTOR (MBusController) {
370  SC_METHOD (MainMethod);
371  for (unsigned int m = 0; m < MASTER_NO; m++) {
372  sensitive << master_cyc[m] << master_stb[m] << master_we[m]
373  << master_cti[m] << master_bte[m] << master_sel[m]
374  << master_adr[m] << master_dat[m];
375  }
376  sensitive << switch_master;
377  };
378 
379  // Functions...
380  void Trace (sc_trace_file * tf, int level = 1);
381 
382 protected:
383  // Processes...
384  void MainMethod ();
385 };
386 
387 
388 // **************** MBusIf **********************
389 
390 typedef enum {
391  BifIdle = 0,
407 } EBusIfState;
408 
409 typedef enum {
417 
418 /*
419 typedef enum {
420  bioNothing = 0, // nothing
421  bioReplace = 7, // replace cache line;
422  bioWriteback = 1, // write cache line back
423  bioFlush = 3, // write back and invalidate afterwards
424  bioInvalidate = 2, // just invalidate, do not write back
425  bioDirectRead = 5, // direct (uncached) read operation
426  bioDirectWrite = 6 // direct (uncached) write operation
427 } EBusIfOperation;
428 */
429 
430 typedef sc_uint<4> EBusIfOperation;
431 #define bioNothing 0 // nothing
432 #define bioWriteback 1 // write back cache line to main memory
433 #define bioInvalidate 2 // just invalidate, do not write back
434 #define bioFlush 3 // write back and invalidate afterwards
435 // 4 undefined so we can use bit 2 to determine if its a cache all operation
436 #define bioWritebackAll 5 // write back whole cache
437 #define bioInvalidateAll 6 // invalidate whole cache
438 #define bioFlushAll 7 // write back and invalidate whole cache
439 #define bioDirectRead 8 // direct (uncached) read operation
440 #define bioDirectWrite 9 // direct (uncached) write operation
441 #define bioReplace 10 // replace cache line
442 
443 #define BUSIF_DATA_REG_NUM (CFG_MEMU_CACHE_BANKS/(CFG_MEMU_BUSIF_WIDTH/32))
444 #define BUSIF_DATA_REG_NUM_LD (CFG_MEMU_CACHE_BANKS_LD-(CFG_MEMU_BUSIF_WIDTH/64))
445 
446 struct SBusIfRegs {
449  bool linelock;
450  sc_uint<4> bsel;
451  sc_uint<32> phys_adr;
452  sc_uint<32> virt_adr;
453  sc_uint<CFG_MEMU_CACHE_BANKS_LD> adr_ofs;
455  sc_uint<CFG_MEMU_BUSIF_WIDTH> idata [BUSIF_DATA_REG_NUM];
456  sc_uint<32> odata [CFG_MEMU_CACHE_BANKS]; // TBD: rename to "rdata...", "wdata..."
457  sc_uint<BUSIF_DATA_REG_NUM_LD> cnt;
458  sc_uint<CFG_MEMU_CACHE_BANKS> banks_left,
461 
462  // MMU related registers
463  bool ac_r;
464  bool ac_w;
465  bool ac_x;
466  bool ac_u;
468  bool paging_en;
469 
470  // Necessary operators for using this structure as signals...
471  // Compare (necessary for signal updates)...
472  bool operator == (const SBusIfRegs &t);
473  // Display...
474  friend ostream& operator << ( ostream& o, const SBusIfRegs &t );
475  // Tracing...
476  friend void sc_trace(sc_trace_file *tf, const SBusIfRegs &t, const std::string &name);
477  };
478 
479 
482  sc_uint<32> adr;
483  bool ack;
484  bool ac_r;
485  bool ac_w;
486  bool ac_x;
487  bool ac_u;
488  bool ac_d;
489  bool ac_a;
490  // Necessary operators for using this structure as signals...
491  // Compare (necessary for signal updates)...
492  bool operator == (const SBusIfMmuRegs &t);
493  // Display...
494  friend ostream& operator << ( ostream& o, const SBusIfMmuRegs &t );
495  // Tracing...
496  friend void sc_trace(sc_trace_file *tf, const SBusIfMmuRegs &t, const std::string &name);
497 };
498 
499 class MBusIf : ::sc_core::sc_module {
500 public:
501  // Ports ...
502  sc_in<bool> clk, reset;
503 
504  // Bus interface (Wishbone)...
505  sc_out<bool> wb_cyc_o; // cycle valid output
506  sc_out<bool> wb_stb_o; // strobe output
507  sc_out<bool> wb_we_o; // indicates write transfer
508  sc_out<sc_uint<3> > wb_cti_o; // cycle type identifier
509  sc_out<sc_uint<2> > wb_bte_o; // burst type extension
510  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > wb_sel_o; // byte select outputs
511  sc_out<sc_uint<32> > wb_adr_o; // address bus outputs
512  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat_o; // output data bus
513 
514  sc_in<bool> wb_ack_i; // normal termination
515  // sc_in<bool> wb_err_i; // termination w/ error
516  // sc_in<bool> wb_rty_i; // termination w/ retry
517  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat_i; // input data bus
518 
519  // Control inputs/outputs...
520  sc_in<EBusIfOperation> busif_op; // all operations are atomic & by default acquire a line lock as needed
521  sc_in<bool> busif_nolinelock; // if set, no line lock is acquired (for write misses: lock is already held by write port)
522  sc_in<sc_uint<4> > busif_bsel; // byte select (only for uncached read & write access)
523  sc_out<bool> busif_busy; // if 0, the BusIF is ready for a new operation
524  // if 0, data writes to the cache (tag & bank) are guaranteed to be completed
525 
526  // Control lines to Tag & Cache banks...
528 
529  // Adress & data busses...
530  sc_in<sc_uint<32> > adr_in;
531  sc_out<sc_uint<32> > adr_out; // to cache banks, tag bank, and r/w ports to determine BUSIF hits
532  // Note: If data width is set to 64Bit bit the 3rd bit of adr_out will be
533  // fixed to 0, to ensure correct hit detection in RPs
534  sc_in<sc_uint<32> > data_in[CFG_MEMU_CACHE_BANKS]; // data from cache banks (bank_rd[n] = 1) or write ports (else)...
535  sc_out<sc_uint<32> > data_out[CFG_MEMU_CACHE_BANKS]; // data read from bus
537  sc_in<SCacheTag> tag_in;
538  sc_out<SCacheTag> tag_out;
539 
540  // Permission lines
541  sc_out<bool> ac_r_out;
542  sc_out<bool> ac_w_out;
543  sc_out<bool> ac_x_out;
544  sc_out<bool> ac_u_out;
545 
546  sc_in<bool> trap_u;
547  sc_in<bool> trap_no_u;
548 
549  // Request & grant lines...
552 
553  // Constructor...
554  SC_HAS_PROCESS (MBusIf);
555  MBusIf (sc_module_name name)
556  : sc_module (name) {
557  SC_METHOD (MainMethod);
558  sensitive << clk.pos();
559  SC_METHOD (TransitionMethod);
560  sensitive << regs;
561  sensitive << ptw_ack << ptw_phys_adr << ptw_ac_a << ptw_ac_d << ptw_ac_r << ptw_ac_w << ptw_ac_x << ptw_ac_u;
562  sensitive << trap_u << trap_no_u;
563  sensitive << busif_op << busif_nolinelock << busif_bsel << adr_in << tag_in;
564  sensitive << gnt_linelock << gnt_tagw << gnt_tagr;
565  sensitive << wb_ack_i << wb_dat_i;
566  sensitive << paging_mode;
567  for (int n = 0; n < CFG_MEMU_CACHE_BANKS; n++)
568  sensitive << data_in[n] << gnt_bank[n];
569  }
570 
571  // To PTW
572  sc_out<sc_uint<32> > ptw_virt_adr; // Translated Physical Address
573  sc_in<sc_uint<32> > ptw_phys_adr; // input data from bus interface
574 
575  sc_out<bool> ptw_req; // Start translation
576  sc_in<bool> ptw_ack; // Address translation successful
577 
578  sc_in<bool> ptw_ac_r;
579  sc_in<bool> ptw_ac_w;
580  sc_in<bool> ptw_ac_x;
581  sc_in<bool> ptw_ac_u;
582  sc_in<bool> ptw_ac_d;
583  sc_in<bool> ptw_ac_a;
584 
585  sc_in<bool> paging_mode;
586 
587  // Functions...
588  void Trace (sc_trace_file * tf, int level = 1);
589 
590  // Processes...
591  void MainMethod ();
592  void TransitionMethod ();
593 protected:
594  // Helpers...
595  void AcceptNewOp ();
596 
597  // BusIf Registers...
598  sc_signal<SBusIfRegs> regs;
599 
600  // Internal BusIf Signals...
601  sc_signal<SBusIfRegs> next_regs;
602 
603  // Special signal for simulation. Only required because the other state signals display non-sense.
604  sc_signal<TWord> state_trace;
605 };
606 
607 
608 
609 // **************** MReadPort *******************
610 
611 typedef enum {
622 
623 
624 class MReadPort : ::sc_core::sc_module {
625 public:
626  // Ports ...
627  sc_in<bool> clk, reset;
628 
629  // With (CPU) port...
630  // - All input ports must be held until 'port_ack' is asserted, at least for one cycle.
631  // - 'port_ack' is issued for exactly one cycle (no full handshake).
632  // - 'port_ack' is issued one cycle before the data is valid (pipelining).
633  // - The next request may be issued at earliest one cycle after 'port_ack' was asserted (which is the same cycle the data is delivered).
634  // - ('port_ack' may be asserted already in the same cycle as the request was issued.) -> minimum latency on cache hit is presently 2 clocks
635  // - If 'port_direct' is set, nothing happens with the cache (i.e. no invalidation).
636  // Hence, 'port_direct' = 0/1 should not be mixed for one adress.
637  sc_in<bool> port_rd, port_direct;
638  sc_out<bool> port_ack;
639  sc_in<sc_uint<32> > port_adr;
640  sc_out<sc_uint<32> > port_data;
641  sc_out<bool> port_ac_r;
642  sc_out<bool> port_ac_x;
643  sc_out<bool> port_ac_u;
644 
645  sc_in<bool> port_lres_scond; // for LR/SC: reserve current adress
646  sc_out<bool> port_scond_ok; // for LR/SC: set, if store-conditional would be sucessful
647 
648  // With BUSIF...
649  sc_in<sc_uint<32> > busif_adr; // adress BUSIF is currently working on (to check for BUSIF hits)
650  sc_in<sc_uint<32> > busif_data; // must be routed here from 'busif.data_out[]' according to 'port_adr'
652  sc_out<EBusIfOperation> busif_op; // This can be replaced by one bit (only 'bioReplace' is invoked)
653  sc_in<bool> busif_busy;
654  sc_in<bool> busif_ac_r;
655  sc_in<bool> busif_ac_x;
656  sc_in<bool> busif_ac_u;
657 
658  // With cache...
659  // - Adress information for tag is routed around this module from 'port_adr', for bank from 'port_adr' AND 'way_out'.
660  sc_out<bool> tag_rd, bank_rd; // 'bank_rd' and 'cache_data' must be routed according to 'port_adr'
661  sc_in<sc_uint<32> > bank_data_in; // must be routed according to 'bank_sel'
662  sc_out<sc_uint<32> > bank_sel;
663  sc_in<SCacheTag> tag_in;
664  sc_out<sc_uint<32> > way_out;
665 
666  // Request & grant lines...
669 
670  // With snoop unit (arbiter)...
671  sc_in<sc_uint<32> > snoop_adr;
672  sc_in<bool> snoop_stb;
673 
674  // Constructor...
675  SC_HAS_PROCESS (MReadPort);
676  MReadPort (sc_module_name name)
677  : sc_module (name) {
678  SC_METHOD (HitMethod);
679  sensitive << port_adr << busif_adr;
680  for (int b = 0; b < CFG_MEMU_CACHE_BANKS; b++)
681  sensitive << busif_data_valid[b];
682  SC_METHOD (TransitionMethod);
683  sensitive << clk.pos ();
684  SC_METHOD (MainMethod);
685  sensitive << reset << state_reg << bank_sel_reg << busif_hit;
686  sensitive << port_rd << port_direct << port_adr << port_lres_scond;
687  sensitive << busif_ac_r << busif_ac_x << busif_ac_u;
688  sensitive << ac_r_reg << ac_x_reg << ac_u_reg;
689  sensitive << busif_data << busif_busy;
690  sensitive << bank_data_in << tag_in;
691  sensitive << gnt_tagr << gnt_busif;
692  sensitive << snoop_adr << snoop_stb;
693  sensitive << link_valid_reg << link_adr_reg;
694  for (int b = 0; b < CFG_MEMU_CACHE_BANKS; b++)
695  sensitive << gnt_bank[b];
696  }
697 
698  // Functions...
699  void Trace (sc_trace_file * tf, int level = 1);
700 
701  // Processes...
702  void HitMethod ();
703  void TransitionMethod ();
704  void MainMethod ();
705 
706 protected:
707  // Registers...
708  sc_signal<EReadportState> state_reg;
709  sc_signal<int> state_trace;
710 
711  sc_signal<sc_uint<32> > bank_sel_reg;
712 
713  sc_signal<sc_uint<32> > link_adr_reg;
714  sc_signal<bool> link_valid_reg;
715  sc_signal<bool> ac_r_reg;
716  sc_signal<bool> ac_x_reg;
717  sc_signal<bool> ac_u_reg;
718 
719 
720  // Internal signals...
721  sc_signal<bool> busif_hit;
722  sc_signal<EReadportState> next_state;
723  sc_signal<sc_uint<32> > next_bank_sel;
724  sc_signal<sc_uint<32> > next_link_adr_reg;
725  sc_signal<bool> next_link_valid_reg;
726  sc_signal<bool> next_ac_r_reg;
727  sc_signal<bool> next_ac_x_reg;
728  sc_signal<bool> next_ac_u_reg;
729 };
730 
731 
732 // **************** MWritePort *******************
733 
734 typedef enum {
753 
754 
755 class MWritePort : ::sc_core::sc_module {
756 public:
757  // Ports ...
758  sc_in<bool> clk, reset;
759 
760  // With (CPU) port...
761  // - All input ports must be held until 'port_ack' is asserted, at least one cycle.
762  // - 'port_ack' is issued for exactly one cycle (no full handshake).
763  // - 'port_ack' may be asserted already in the same cycle as the request was issued.
764  // - The next request may be issued at earliest one cycle after 'port_ack' was asserted. (TBD: allow in the ACK cycle?)
765  // - If 'port_direct' is set, nothing happens with the cache (i.e. no invalidation).
766  // Hence, 'port_direct' = 0/1 should not be mixed for one adress.
767  sc_in<bool> port_wr, port_direct;
768  sc_in<sc_uint<4> > port_bsel;
769  sc_out<bool> port_ack;
770  sc_out<bool> port_ac_w;
771  sc_in<bool> port_trap_u;
772  sc_in<bool> port_trap_no_u;
773 
774  sc_in<sc_uint<3> > port_cache_op; // Cache control; | all | writeback | invalidate |
775 
776  sc_in<sc_uint<32> > port_adr;
777  sc_in<sc_uint<32> > port_data;
778 
779  sc_in<bool> port_lres_scond; // for LR/SC: store only if lres_valid
780  sc_in<bool> port_scond_ok;
781 
782  // With BUSIF...
783  // - There is no direct transfer except for uncached memory access.
784  sc_in<sc_uint<32> > busif_adr; // adress BUSIF is currently working on (to check for BUSIF hits)
785  sc_out<EBusIfOperation> busif_op;
786  sc_out<bool> busif_nolinelock; // if set, no line lock is acquired (for write misses: lock is already held by write port) (TBD: eliminate this signal)
787  sc_in<bool> busif_busy;
788  sc_in<bool> busif_ac_w;
789 
790  // With cache...
791  // - Adress information for tag must be routed from 'port_adr', for the banks from 'port_adr' and 'tag_out.way'.
792  sc_out<bool> tag_rd, tag_wr, bank_rd, bank_wr; // 'bank_rd', 'bank_wr' must be routed according to 'port_adr'
793  sc_in<sc_uint<32> > bank_data_in; // must be routed according to 'port_adr'
794  sc_out<sc_uint<32> > bank_data_out; // must be routed according to 'port_adr'
795  sc_out<sc_uint<4> > bank_bsel;
796  sc_in<SCacheTag> tag_in;
797  sc_out<SCacheTag> tag_out;
798 
799  // Request & grant lines...
802 
803  // Constructor...
804  SC_HAS_PROCESS (MWritePort);
805  MWritePort (sc_module_name name)
806  : sc_module (name) {
807  SC_METHOD (TransitionMethod);
808  sensitive << clk.pos ();
809  SC_METHOD (MainMethod);
810  sensitive << reset << state_reg;
813  sensitive << busif_adr << busif_busy << bank_data_in << busif_ac_w << tag_in;
814  sensitive << gnt_linelock << gnt_tagr << gnt_tagw << gnt_busif;
815  sensitive << port_trap_u << port_trap_no_u;
816  sensitive << tag_reg << data_reg;
817  for (int b = 0; b < CFG_MEMU_CACHE_BANKS; b++)
818  sensitive << gnt_bank[b];
819  }
820 
821  // Functions...
822  void Trace (sc_trace_file * tf, int level = 1);
823 
824  // Processes...
825  void TransitionMethod ();
826  void MainMethod ();
827 
828 protected:
829  // Registers...
830  sc_signal<EWritePortState> state_reg;
831  sc_signal<int> state_trace;
832 
833  sc_signal<SCacheTag> tag_reg;
834  sc_signal<sc_uint<32> > data_reg;
835 
836  // Internal signals..
837  sc_signal<EWritePortState> next_state;
838  sc_signal<SCacheTag> next_tag_reg;
839  sc_signal<sc_uint<32> > next_data_reg;
840 };
841 
842 
843 // **************** MArbiter ********************
844 
845 
846 class MArbiter : ::sc_core::sc_module {
847 public:
848  // Ports ...
849  sc_in<bool> clk, reset;
850 
852  way_wp[CFG_MEMU_WPORTS]; // (way+index) adresses from various ports;
853  // must be kept constant as long as 'req_*' lines are held
854  sc_out<sc_uint<32> > wiadr_bank[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]; // adress lines to the banks
855 
856  // Write snooping...
857  sc_out<sc_uint<32> > snoop_adr;
858  sc_out<bool> snoop_stb[CFG_MEMU_WPORTS];
859 
860  // Line lock...
861  // - Implements mutex for a single cache line (tag + all data banks).
862  // - Writers are supposed to acquire a line lock.
863  // - Reader do not acquire anything => Writers must perform their actions in a safe order.
864  // - if a line lock request is held, the associated address must not change
865  // - A line lock may be released during the clock cycle that the last bank/tag access is made,
866  // given that the bank/tag lock is still held. This allows faster write cycles without write
867  // port monopolizing a line lock (keeping it permanently up).
870 
871  // Tag RAM...
872  // - Tag RAM must have CFG_NUT_CPU_CORES ports.
873  // - Each port is reserved for one CPU (three ports: RP #n, RP #CFG_NUT_CPU_CORES+n, WP #n).
874  // - BUSIF uses port #CFG_NUT_CPU_CORES-1.
875  // - Arbiter provides:
876  // a) Write-/Read-Lock (a write-lock excludes all readers)
877  // b) Port arbitration: Multiple readers are allowed, but only one per port (see above)
878  // c) Priority selection amoung a port: 0. BUSIF (if applicable), 1. Data read, 2. Insn Read, 3. Data Write
879  // EXAMINE: Would two ports/CPU bring speed improvement? Would a seperate port for BUSIF bring speed improvement?
880  // - The tag RAM arbitration is also used to prevent writers from replacing/changing a cache line
881  // while it is read during a cache read hit. Hence, a reader must keep its 'tagr' lock until its bank access
882  // is completed, too. This is not necessary, if a line lock is held (i.e. for cache line reading during a write miss).
883  sc_in<bool> tagram_ready;
887 
888  // Bank RAMs...
889  // - All ports of CPU n must be linked to port n % CFG_MEMU_BANK_RAM_PORTS of each bank RAM.
890  // - The BUSIF is linked to port #(CFG_MEMU_BANK_RAM_PORTS-1).
891  // - Multiple usually conflicting grant signals may be set, if the adresses match.
892  // - As long as a request signal is set, the adress must not change!
893  // - Amoung write ports and the BUSIF, only one grant will be given to avoid writing conflicts.
898 
899  // BUSIF...
902  // select/routing information can be derived from grant lines (only one is set at a time)
903 
904  // Note on deadlock prevention:
905  // 1. Requests/grants must always in the following order (-> break cyclic wait condition):
906  // busif < linelock < tagr/tagw < bank
907  // 2. (corollary to 1.) R/W ports must not request anything when waiting for BusIF (i.e. 'busif_busy')
908  // 3. tag/bank access may never be requested in a hold-and-wait manner: Either request simultaneously or use & complete serially.
909 
910  // Constructor...
911  SC_HAS_PROCESS (MArbiter);
912  MArbiter (sc_module_name name)
913  : sc_module (name) {
914  int n, b;
915 
916  SC_METHOD (LineLockMethod);
917  sensitive << req_busif_linelock << wiadr_busif;
918  sensitive << linelock_sel_out;
919  for (n = 0; n < CFG_MEMU_WPORTS; n++)
920  sensitive << req_wp_linelock[n] << adr_wp[n];
921  SC_METHOD (TagMethod);
922  sensitive << tagram_ready << req_busif_tagr << req_busif_tagw;
923  sensitive << tagr_reg << tagw_reg << req_tagw_reg;
924  for (n = 0; n < CFG_MEMU_RPORTS; n++)
925  sensitive << req_rp_tagr[n];
926  for (n = 0; n < CFG_MEMU_WPORTS; n++)
927  sensitive << req_wp_tagr[n] << req_wp_tagw[n];
928  SC_METHOD (BankMethod);
929  sensitive << wiadr_busif;
930  for (n = 0; n < CFG_MEMU_RPORTS; n++)
931  sensitive << wiadr_rp[n];
932  for (n = 0; n < CFG_MEMU_WPORTS; n++)
933  sensitive << adr_wp[n] << way_wp[n];
934  for (b = 0; b < CFG_MEMU_CACHE_BANKS; b++) {
935  sensitive << req_busif_bank[b];
936  for (n = 0; n < CFG_MEMU_BANK_RAM_PORTS; n++)
937  sensitive << bank_sel_out[b][n];
938  for (n = 0; n < CFG_MEMU_RPORTS; n++)
939  sensitive << req_rp_bank[n][b];
940  for (n = 0; n < CFG_MEMU_WPORTS; n++)
941  sensitive << req_wp_bank[n][b];
942  }
943  SC_METHOD (BusIfMethod);
944  sensitive << busif_reg;
945  for (n = 0; n < CFG_MEMU_RPORTS; n++)
946  sensitive << req_rp_busif[n];
947  for (n = 0; n < CFG_MEMU_WPORTS; n++)
948  sensitive << req_wp_busif[n];
949  sensitive << busif_sel_out;
950  SC_METHOD (SnoopMethod);
951  sensitive << next_linelock_reg;
952  for (n = 0; n < CFG_MEMU_WPORTS; n++)
953  sensitive << adr_wp[n];
954  SC_METHOD (PrioCPUMethod);
955  sensitive << counter_reg;
956 
957  SC_CTHREAD (TransitionThread, clk.pos ());
958  reset_signal_is (reset, true);
959 
960  for (int b = 0; b < CFG_MEMU_CACHE_BANKS; b++) {
961  // Generate the Selector or Passthrough for the Bank BusIf Arbitration...
962  if (CFG_NUT_CPU_CORES >= 2 || CFG_MEMU_BANK_RAM_PORTS == 1) {
963  // The BankBusIf step has the BusIF and all other CPUs as input
964  BankSelector_t *sel = new BankSelector_t(std::string("BankBusIfSel" + std::to_string (b)).c_str());
965  sel->clk (clk);
966  sel->reset (reset);
967  sel->f_in (bank_sel_in[b][CFG_MEMU_BANK_RAM_PORTS-1][0]); // BusIf
968  sel->s_in (bank_sel_in[b][CFG_MEMU_BANK_RAM_PORTS-1][1]);
970  sel->prio (cpu_prio);
971  bank_sel[b][CFG_MEMU_BANK_RAM_PORTS-1] = sel;
972 
973  } else /*if (CFG_NUT_CPU_CORES < 2)*/ {
974  BankSelectorPass_t *pass = new BankSelectorPass_t(std::string("BankBusIfSel" + std::to_string (b)).c_str());
975  pass->f_in (bank_sel_in[b][CFG_MEMU_BANK_RAM_PORTS-1][0]); // BusIf
977  bank_sel[b][CFG_MEMU_BANK_RAM_PORTS-1] = pass;
978  }
979 
980  // Generate the Selector or Passthrough for the Bank CPU Arbitration for 2 BRAM ports ...
981  if (CFG_MEMU_BANK_RAM_PORTS > 1) {
982  if (CFG_NUT_CPU_CORES >= 4) {
983  // The Bank step has the BusIF and all other CPUs as input
984  BankSelector_t *sel = new BankSelector_t(std::string("BankSel" + std::to_string (b)).c_str());
985  sel->clk (clk);
986  sel->reset (reset);
987  sel->f_in (bank_sel_in[b][0][0]); // CePU
988  sel->s_in (bank_sel_in[b][0][1]);
989  sel->out (bank_sel_out[b][0]);
990  sel->prio (cpu_prio);
991  bank_sel[b][0] = sel;
992 
993  } else /*if (CFG_NUT_CPU_CORES < 4)*/ {
994  BankSelectorPass_t *pass = new BankSelectorPass_t(std::string("BankSel" + std::to_string (b)).c_str());
995  pass->f_in (bank_sel_in[b][0][0]); // CePU
996  pass->out (bank_sel_out[b][0]);
997  bank_sel[b][0] = pass;
998  }
999  }
1000  }
1001 
1002 
1003  // Generate the Selector or Passthrough for the BusIf Arbitration...
1004  if (CFG_NUT_CPU_CORES >= 2) {
1005  // The step has the CePU and all other CoPUs as input
1006  BusifSelector_t *sel = new BusifSelector_t("BusIfSel");
1007  sel->clk (clk);
1008  sel->reset (reset);
1009  sel->f_in (busif_sel_in[0]); //CePU
1010  sel->s_in (busif_sel_in[1]);
1011  sel->out (busif_sel_out);
1012  sel->prio (cpu_prio);
1013  busif_sel = sel;
1014  }
1015  if (CFG_NUT_CPU_CORES < 2) {
1016  BusIfSelectorPass_t *pass = new BusIfSelectorPass_t("BusIfSel");
1017  pass->f_in (busif_sel_in[0]); //CePU
1018  pass->out (busif_sel_out);
1019  busif_sel = pass;
1020  }
1021 
1022  // Generate the Selector or Passthrough for the LineLock Arbitration...
1023  if (CFG_NUT_CPU_CORES >= 2) {
1024  // The step has the CePU WPORT and all other CoPUs WPORTs as input
1025  LineLockSelector_t *sel = new LineLockSelector_t("LineLockSel");
1026  sel->clk (clk);
1027  sel->reset (reset);
1028  sel->f_in (linelock_sel_in[0]); //CePU
1029  sel->s_in (linelock_sel_in[1]);
1030  sel->out (linelock_sel_out);
1031  sel->prio (cpu_prio);
1032  linelock_sel = sel;
1033  }
1034  if (CFG_NUT_CPU_CORES < 2) {
1035  LineLockSelectorPass_t *pass = new LineLockSelectorPass_t("LineLockSel");
1036  pass->f_in (linelock_sel_in[0]); //CePU
1037  pass->out (linelock_sel_out);
1038  linelock_sel = pass;
1039  }
1040  }
1041  ~MArbiter ();
1042 
1043  // Functions...
1044  void Trace (sc_trace_file * tf, int level = 1);
1045 
1046  // Processes...
1047  void LineLockMethod ();
1048  void TagMethod ();
1049  void BankMethod ();
1050  void BusIfMethod ();
1051  void SnoopMethod ();
1052  void PrioCPUMethod ();
1053 
1054  void TransitionThread ();
1055 
1056 
1057 protected:
1058 
1059  // Helpers...
1060  int GetPrioCpu ();
1061 
1062  // Registers...
1063  sc_signal<sc_uint<16> > counter_reg;
1064  sc_signal<sc_uint<CFG_MEMU_WPORTS + 1> > linelock_reg;
1065  sc_signal<sc_uint<CFG_MEMU_RPORTS + CFG_MEMU_WPORTS + 1> > tagr_reg;
1066  sc_signal<sc_uint<CFG_MEMU_WPORTS + 1> > req_tagw_reg;
1067  sc_signal<sc_uint<CFG_MEMU_WPORTS + 1> > tagw_reg;
1069  sc_signal<sc_uint<CFG_MEMU_RPORTS + CFG_MEMU_WPORTS> > busif_reg;
1070 
1071  // Signals...
1072  sc_signal<sc_uint<CFG_MEMU_WPORTS + 1> > next_linelock_reg;
1073  sc_signal<sc_uint<CFG_MEMU_RPORTS + CFG_MEMU_WPORTS + 1> > next_tagr_reg;
1074  sc_signal<sc_uint<CFG_MEMU_WPORTS + 1> > next_req_tagw_reg;
1075  sc_signal<sc_uint<CFG_MEMU_WPORTS + 1> > next_tagw_reg;
1077  sc_signal<sc_uint<CFG_MEMU_RPORTS + CFG_MEMU_WPORTS> > next_busif_reg;
1078 
1079  sc_signal<sc_uint<MAX(1, CFG_NUT_CPU_CORES_LD)> > cpu_prio;
1080 
1081  // BusIf Arbitration Signals...
1084  sc_module* busif_sel;
1085 
1088 
1089  // LineLock Arbitration Signals...
1092  sc_module* linelock_sel;
1093 
1094  sc_signal<SSelectorIO<1, CFG_MEMU_WPORTS> > linelock_sel_out;
1095  sc_signal<SSelectorIO<1, CFG_MEMU_WPORTS> > linelock_sel_in [2];
1096 
1097  // Bank Arbitration Signals...
1098  static const bool SINGLE_CPU = CFG_NUT_CPU_CORES == 1;
1102 
1105 
1106 };
1107 
1108 
1109 // **************** MMemu ***********************
1110 
1111 class MMemu : ::sc_core::sc_module {
1112 public:
1113  // Ports ...
1114  sc_in<bool> clk, reset;
1115 
1116  // Bus interface (Wishbone)...
1117  sc_out<bool> wb_cyc_o; // cycle valid output
1118  sc_out<bool> wb_stb_o; // strobe output
1119  sc_out<bool> wb_we_o; // indicates write transfer
1120  sc_out<sc_uint<3> > wb_cti_o; // cycle type identifier
1121  sc_out<sc_uint<2> > wb_bte_o; // burst type extension
1122  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > wb_sel_o; // byte select outputs
1123  sc_out<sc_uint<32> > wb_adr_o; // address bus outputs
1124  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat_o; // output data bus
1125 
1126  sc_in<bool> wb_ack_i; // normal termination
1127  // sc_in<bool> wb_err_i; // termination w/ error
1128  // sc_in<bool> wb_rty_i; // termination w/ retry
1129  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat_i; // input data bus
1130 
1131  // Read ports...
1132  // ports 0 .. WPORT-1 are considerd to be data ports, the others to be instruction ports (with lower priority)
1134  sc_in<sc_uint<4> > rp_bsel[CFG_MEMU_RPORTS];
1136  sc_out<bool> rp_ack[CFG_MEMU_RPORTS];
1137  sc_in<sc_uint<32> > rp_adr[CFG_MEMU_RPORTS];
1138  sc_out<sc_uint<32> > rp_data[CFG_MEMU_RPORTS];
1140  // Write ports...
1142  sc_in<sc_uint<4> > wp_bsel[CFG_MEMU_WPORTS];
1144  sc_out<bool> wp_ack[CFG_MEMU_WPORTS];
1147  sc_in<sc_uint<3> > wp_cache_op[CFG_MEMU_WPORTS];
1148  sc_in<sc_uint<32> > wp_adr[CFG_MEMU_WPORTS];
1149  sc_in<sc_uint<32> > wp_data[CFG_MEMU_WPORTS];
1150  sc_out<bool> wp_ac_w[CFG_MEMU_WPORTS];
1152 
1153 
1154  // MMU related ports...
1155  sc_in<sc_uint<20> > root_ppn;
1156  sc_in<bool> tlb_flush;
1157 
1158  // Constructor/Destructor...
1159  SC_HAS_PROCESS (MMemu);
1160  MMemu (sc_module_name name)
1161  : sc_module (name) {
1162  InitSubmodules ();
1163  SC_METHOD (TransitionMethod);
1164  sensitive << clk.pos ();
1166  }
1168 
1169  // Functions...
1170  void Trace (sc_trace_file * tf, int levels = 1);
1171 
1172  // Processes...
1173  void TransitionMethod ();
1174  void InterconnectMethod ();
1175 
1176  // Submodules...
1179  MBusController *busController;
1181  MPtw *ptw;
1186 
1187 protected:
1188  // Tag RAM...
1190  sc_signal<sc_uint<32> > tagram_adr[TR_PORTS];
1191  sc_signal<sc_uint<32> > tagram_wadr[TR_PORTS];
1193 
1194  // Bank RAM...
1200 
1201  // BusController
1202  sc_signal<bool> master_cyc[MASTER_NO]; // cycle valid output
1203  sc_signal<bool> master_stb[MASTER_NO]; // strobe output
1204  sc_signal<bool> master_we[MASTER_NO]; // indicates write transfer
1205  sc_signal<sc_uint<3> > master_cti[MASTER_NO]; // cycle type identifier
1206  sc_signal<sc_uint<2> > master_bte[MASTER_NO]; // burst type extension
1207  sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > master_sel[MASTER_NO]; // byte select outputs
1208  sc_signal<sc_uint<32> > master_adr[MASTER_NO]; // address bus outputs
1209  sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > master_dat[MASTER_NO]; // output data bus
1210  sc_signal<bool> switch_master;
1211 
1212  // BUSIF...
1213  sc_signal<EBusIfOperation> busif_op;
1214  sc_signal<bool> busif_nolinelock, busif_busy;
1220  sc_signal<SCacheTag> busif_tag_in, busif_tag_out;
1221  sc_signal<sc_uint<4> > busif_bsel;
1223  sc_signal<bool> busif_trap_u, busif_trap_no_u;
1224  sc_signal<bool> busif_paging;
1225 
1226  // Read ports...
1227  sc_signal<sc_uint<32> > rp_busif_data_reg[CFG_MEMU_BUSIF_WIDTH/32]; // register to delay BusIF data for one clock cycle in accordance with the protocol
1228  sc_signal<sc_uint<32> > rp_busif_data[CFG_MEMU_RPORTS];
1229  sc_signal<EBusIfOperation> rp_busif_op[CFG_MEMU_RPORTS];
1231  sc_signal<SCacheTag> rp_tag_in[CFG_MEMU_RPORTS];
1232  sc_signal<sc_uint<32> > rp_way_out[CFG_MEMU_RPORTS];
1233  sc_signal<sc_uint<32> > rp_bank_data_in[CFG_MEMU_RPORTS];
1234  sc_signal<sc_uint<32> > rp_bank_sel[CFG_MEMU_RPORTS];
1235 
1236  // Write ports...
1237  sc_signal<EBusIfOperation> wp_busif_op[CFG_MEMU_WPORTS];
1242  sc_signal<sc_uint<4> > wp_bank_bsel[CFG_MEMU_WPORTS];
1243 
1244  // Arbiter: request/grant signals (find comments in 'MArbiter')...
1247 
1254 
1259 
1262 
1263  // Arbiter: other signals ...
1265  sc_signal<sc_uint<32> > snoop_adr;
1266  sc_signal<bool> snoop_stb[CFG_MEMU_WPORTS];
1267 
1268  // PTW
1269  sc_signal<sc_uint<32> > ptw_phys_adr;
1270  sc_signal<sc_uint<32> > ptw_virt_adr;
1271  sc_signal<bool> ptw_req;
1272  sc_signal<bool> ptw_ack;
1273 
1274  sc_signal<bool> ptw_ac_r;
1275  sc_signal<bool> ptw_ac_w;
1276  sc_signal<bool> ptw_ac_x;
1277  sc_signal<bool> ptw_ac_u;
1278  sc_signal<bool> ptw_ac_d;
1279  sc_signal<bool> ptw_ac_a;
1280 
1281  // TLB
1282  sc_signal<bool> tlb_req, tlb_wr;
1283  sc_signal<sc_uint<20> > tlb_va_o;
1284  sc_signal<sc_uint<20> > tlb_pa_o;
1285  sc_signal<bool> tlb_superpage_o;
1286  sc_signal<bool> tlb_ac_r_o;
1287  sc_signal<bool> tlb_ac_w_o;
1288  sc_signal<bool> tlb_ac_x_o;
1289  sc_signal<bool> tlb_ac_u_o;
1290  sc_signal<bool> tlb_ac_d_o;
1291  sc_signal<bool> tlb_ac_a_o;
1292 
1293  sc_signal<bool> tlb_superpage_i;
1294  sc_signal<sc_uint<20> > tlb_adr_i;
1295  sc_signal<bool> tlb_hit;
1296  sc_signal<bool> tlb_miss;
1297 
1298  sc_signal<bool> tlb_ac_r_i;
1299  sc_signal<bool> tlb_ac_w_i;
1300  sc_signal<bool> tlb_ac_x_i;
1301  sc_signal<bool> tlb_ac_u_i;
1302  sc_signal<bool> tlb_ac_d_i;
1303  sc_signal<bool> tlb_ac_a_i;
1304 
1305  // Methods...
1306  void InitSubmodules ();
1307  void FreeSubmodules ();
1308  void InitInterconnectMethod ();
1309 };
1310 
1311 
1312 #endif
Helpers, Makros and performance measuring Classes used in most ParaNut files.
Definition: memu.h:846
sc_in< bool > req_rp_bank[CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:895
sc_signal< sc_uint< CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+1 > > next_tagr_reg
Definition: memu.h:1073
sc_in< bool > req_wp_busif[CFG_MEMU_WPORTS]
Definition: memu.h:900
int GetPrioCpu()
Definition: memu.cpp:2354
sc_signal< SSelectorIO< CFG_MEMU_CACHE_WAYS_LD+CFG_MEMU_CACHE_SETS_LD,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS > > bank_sel_out[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1103
sc_signal< sc_uint< 16 > > counter_reg
Definition: memu.h:1063
sc_in< bool > req_rp_busif[CFG_MEMU_RPORTS]
Definition: memu.h:900
sc_out< bool > gnt_wp_busif[CFG_MEMU_WPORTS]
Definition: memu.h:901
sc_out< bool > gnt_rp_busif[CFG_MEMU_RPORTS]
Definition: memu.h:901
sc_in< sc_uint< 32 > > wiadr_busif
Definition: memu.h:851
sc_module * linelock_sel
Definition: memu.h:1092
sc_in< bool > req_busif_linelock
Definition: memu.h:868
sc_signal< SSelectorIO< 1,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+1)> > busif_sel_in[2]
Definition: memu.h:1087
sc_in< bool > clk
Definition: memu.h:849
sc_in< bool > req_wp_linelock[CFG_MEMU_WPORTS]
Definition: memu.h:868
MSelectorPass< CFG_MEMU_CACHE_WAYS_LD+CFG_MEMU_CACHE_SETS_LD,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS > BankSelectorPass_t
Definition: memu.h:1099
sc_in< bool > req_busif_tagr
Definition: memu.h:884
~MArbiter()
Definition: memu.cpp:1957
sc_in< bool > reset
Definition: memu.h:849
sc_module * bank_sel[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1101
sc_out< bool > gnt_wp_tagr_r[CFG_MEMU_WPORTS]
Definition: memu.h:886
static const bool SINGLE_CPU
Definition: memu.h:1098
sc_signal< SSelectorIO< 1,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+1)> > busif_sel_out
Definition: memu.h:1086
sc_signal< sc_uint< CFG_MEMU_WPORTS+1 > > req_tagw_reg
Definition: memu.h:1066
sc_out< bool > gnt_busif_linelock
Definition: memu.h:869
sc_out< bool > snoop_stb[CFG_MEMU_WPORTS]
Definition: memu.h:858
sc_out< bool > gnt_busif_tagw
Definition: memu.h:885
MArbiter(sc_module_name name)
Definition: memu.h:912
sc_signal< SSelectorIO< 1, CFG_MEMU_WPORTS > > linelock_sel_in[2]
Definition: memu.h:1095
MSelector< 1, CFG_MEMU_WPORTS > LineLockSelector_t
Definition: memu.h:1091
sc_signal< sc_uint< CFG_MEMU_RPORTS+CFG_MEMU_WPORTS > > busif_reg
Definition: memu.h:1069
void BusIfMethod()
Definition: memu.cpp:2249
void BankMethod()
Definition: memu.cpp:2124
sc_out< bool > gnt_wp_tagr[CFG_MEMU_WPORTS]
Definition: memu.h:885
sc_in< sc_uint< 32 > > adr_wp[CFG_MEMU_WPORTS]
Definition: memu.h:851
sc_signal< sc_uint< CFG_MEMU_RPORTS+CFG_MEMU_WPORTS > > next_busif_reg
Definition: memu.h:1077
MSelector< 1,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+1)> BusifSelector_t
Definition: memu.h:1083
MSelectorPass< 1, CFG_MEMU_WPORTS > LineLockSelectorPass_t
Definition: memu.h:1090
sc_out< bool > gnt_wp_linelock[CFG_MEMU_WPORTS]
Definition: memu.h:869
void PrioCPUMethod()
Definition: memu.cpp:1962
sc_module * busif_sel
Definition: memu.h:1084
sc_signal< sc_uint< CFG_MEMU_WPORTS+1 > > tagw_reg
Definition: memu.h:1067
sc_in< bool > req_rp_tagr[CFG_MEMU_RPORTS]
Definition: memu.h:884
sc_signal< sc_uint< CFG_MEMU_WPORTS+1 > > next_req_tagw_reg
Definition: memu.h:1074
sc_in< bool > req_wp_tagw[CFG_MEMU_WPORTS]
Definition: memu.h:884
sc_signal< SSelectorIO< 1, CFG_MEMU_WPORTS > > linelock_sel_out
Definition: memu.h:1094
sc_signal< SSelectorIO< CFG_MEMU_CACHE_WAYS_LD+CFG_MEMU_CACHE_SETS_LD,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS > > bank_sel_in[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS][2]
Definition: memu.h:1104
void LineLockMethod()
Definition: memu.cpp:1966
sc_signal< sc_uint< CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+1 > > tagr_reg
Definition: memu.h:1065
sc_out< bool > gnt_wp_tagw_r[CFG_MEMU_WPORTS]
Definition: memu.h:886
sc_signal< sc_uint< CFG_MEMU_WPORTS+1 > > linelock_reg
Definition: memu.h:1064
sc_signal< sc_uint< CFG_MEMU_WPORTS+1 > > next_linelock_reg
Definition: memu.h:1072
sc_in< sc_uint< 32 > > wiadr_rp[CFG_MEMU_RPORTS]
Definition: memu.h:851
sc_out< bool > gnt_rp_bank[CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:897
sc_out< bool > gnt_busif_tagr
Definition: memu.h:885
sc_out< bool > gnt_rp_tagr[CFG_MEMU_RPORTS]
Definition: memu.h:885
sc_out< bool > gnt_busif_tagw_r
Definition: memu.h:886
sc_in< bool > tagram_ready
Definition: memu.h:883
MSelector< CFG_MEMU_CACHE_WAYS_LD+CFG_MEMU_CACHE_SETS_LD,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS > BankSelector_t
Definition: memu.h:1100
sc_in< bool > req_wp_bank[CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:894
MSelectorPass< 1,(CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+1)> BusIfSelectorPass_t
Definition: memu.h:1082
sc_out< bool > gnt_wp_tagw[CFG_MEMU_WPORTS]
Definition: memu.h:885
void Trace(sc_trace_file *tf, int level=1)
Definition: memu.cpp:1849
sc_in< bool > req_busif_tagw
Definition: memu.h:884
sc_signal< sc_uint<((CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+(CFG_NUT_CPU_CORES_LD==0))/CFG_MEMU_BANK_RAM_PORTS)+1 > > bank_reg[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1068
sc_out< bool > gnt_busif_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:896
sc_out< sc_uint< 32 > > wiadr_bank[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:854
sc_in< sc_uint< 32 > > way_wp[CFG_MEMU_WPORTS]
Definition: memu.h:852
sc_out< bool > gnt_busif_tagr_r
Definition: memu.h:886
sc_signal< sc_uint<((CFG_MEMU_RPORTS+CFG_MEMU_WPORTS+(CFG_NUT_CPU_CORES_LD==0))/CFG_MEMU_BANK_RAM_PORTS)+1 > > next_bank_reg[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1076
sc_out< sc_uint< 32 > > snoop_adr
Definition: memu.h:857
sc_signal< sc_uint< MAX(1, CFG_NUT_CPU_CORES_LD)> > cpu_prio
Definition: memu.h:1079
sc_out< bool > gnt_rp_tagr_r[CFG_MEMU_RPORTS]
Definition: memu.h:886
sc_signal< sc_uint< CFG_MEMU_WPORTS+1 > > next_tagw_reg
Definition: memu.h:1075
sc_in< bool > req_busif_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:894
sc_in< bool > req_wp_tagr[CFG_MEMU_WPORTS]
Definition: memu.h:884
void TagMethod()
Definition: memu.cpp:2029
void TransitionThread()
Definition: memu.cpp:2363
sc_out< bool > gnt_wp_bank[CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:896
void SnoopMethod()
Definition: memu.cpp:2330
Definition: memu.h:312
sc_in< sc_uint< 4 > > wen[CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:319
sc_in< sc_uint< 32 > > wdata[CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:322
sc_uint< 32 > ram_[CFG_MEMU_CACHE_SETS *CFG_MEMU_CACHE_WAYS]
Definition: memu.h:337
sc_in< sc_uint< 32 > > wiadr[CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:321
MBankRam(sc_module_name name)
Definition: memu.h:327
sc_in< bool > wr[CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:317
void Trace(sc_trace_file *tf, int level=1)
Definition: memu.cpp:160
sc_in< bool > clk
Definition: memu.h:315
sc_in< bool > rd[CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:317
void MainThread()
Definition: memu.cpp:178
sc_out< sc_uint< 32 > > rdata[CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:323
Definition: memu.h:499
sc_in< sc_uint< 32 > > adr_in
Definition: memu.h:530
sc_signal< TWord > state_trace
Definition: memu.h:604
sc_in< sc_uint< 4 > > busif_bsel
Definition: memu.h:522
sc_in< bool > ptw_ac_u
Definition: memu.h:581
sc_in< bool > wb_ack_i
Definition: memu.h:514
sc_in< bool > ptw_ack
Definition: memu.h:576
sc_out< bool > req_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:550
sc_in< bool > gnt_tagw
Definition: memu.h:551
sc_in< bool > trap_u
Definition: memu.h:546
sc_out< bool > bank_wr[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:527
sc_out< bool > req_tagw
Definition: memu.h:550
sc_out< bool > wb_cyc_o
Definition: memu.h:505
sc_out< bool > ac_r_out
Definition: memu.h:541
sc_out< sc_uint< 2 > > wb_bte_o
Definition: memu.h:509
sc_in< bool > clk
Definition: memu.h:502
void MainMethod()
Definition: memu.cpp:578
sc_out< bool > wb_we_o
Definition: memu.h:507
sc_in< bool > gnt_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:551
sc_in< bool > trap_no_u
Definition: memu.h:547
sc_out< bool > ac_w_out
Definition: memu.h:542
sc_in< bool > ptw_ac_a
Definition: memu.h:583
sc_out< bool > req_tagr
Definition: memu.h:550
sc_in< bool > ptw_ac_r
Definition: memu.h:578
sc_out< bool > ac_u_out
Definition: memu.h:544
sc_out< sc_uint< 32 > > ptw_virt_adr
Definition: memu.h:572
sc_out< bool > tag_wr
Definition: memu.h:527
sc_out< bool > ptw_req
Definition: memu.h:575
sc_out< bool > busif_busy
Definition: memu.h:523
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > wb_sel_o
Definition: memu.h:510
void AcceptNewOp()
sc_out< bool > wb_stb_o
Definition: memu.h:506
sc_out< sc_uint< 32 > > adr_out
Definition: memu.h:531
sc_in< bool > gnt_tagr
Definition: memu.h:551
sc_out< SCacheTag > tag_out
Definition: memu.h:538
sc_in< bool > paging_mode
Definition: memu.h:585
sc_out< bool > tag_rd_way
Definition: memu.h:527
sc_out< sc_uint< 32 > > wb_adr_o
Definition: memu.h:511
sc_signal< SBusIfRegs > next_regs
Definition: memu.h:601
sc_in< EBusIfOperation > busif_op
Definition: memu.h:520
sc_in< bool > ptw_ac_x
Definition: memu.h:580
sc_out< bool > req_linelock
Definition: memu.h:550
sc_in< bool > ptw_ac_w
Definition: memu.h:579
sc_out< bool > tag_rd
Definition: memu.h:527
void TransitionMethod()
Definition: memu.cpp:605
sc_in< sc_uint< 32 > > data_in[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:534
sc_in< bool > busif_nolinelock
Definition: memu.h:521
sc_out< sc_uint< 3 > > wb_cti_o
Definition: memu.h:508
sc_out< bool > data_out_valid[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:536
sc_signal< SBusIfRegs > regs
Definition: memu.h:598
sc_in< bool > ptw_ac_d
Definition: memu.h:582
sc_in< SCacheTag > tag_in
Definition: memu.h:537
sc_in< bool > reset
Definition: memu.h:502
MBusIf(sc_module_name name)
Definition: memu.h:555
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_o
Definition: memu.h:512
sc_out< bool > bank_rd[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:527
void Trace(sc_trace_file *tf, int level=1)
Definition: memu.cpp:508
sc_out< sc_uint< 32 > > data_out[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:535
sc_in< bool > gnt_linelock
Definition: memu.h:551
sc_in< sc_uint< 32 > > ptw_phys_adr
Definition: memu.h:573
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_i
Definition: memu.h:517
sc_out< bool > ac_x_out
Definition: memu.h:543
Definition: memu.h:1111
sc_in< sc_uint< 32 > > wp_adr[CFG_MEMU_WPORTS]
Definition: memu.h:1148
sc_signal< bool > busif_bank_wr[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1216
sc_signal< bool > gnt_wp_bank[CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1257
sc_signal< bool > busif_tag_rd_way
Definition: memu.h:1215
sc_in< bool > wb_ack_i
Definition: memu.h:1126
sc_signal< bool > rp_tag_rd[CFG_MEMU_RPORTS]
Definition: memu.h:1230
sc_signal< bool > busif_trap_no_u
Definition: memu.h:1223
sc_signal< bool > tlb_ac_u_o
Definition: memu.h:1289
sc_signal< bool > tagram_wr[TR_PORTS]
Definition: memu.h:1189
MArbiter * arbiter
Definition: memu.h:1183
sc_in< bool > rp_direct[CFG_MEMU_RPORTS]
Definition: memu.h:1133
sc_out< bool > rp_ack[CFG_MEMU_RPORTS]
Definition: memu.h:1136
sc_signal< bool > busif_ac_w
Definition: memu.h:1222
sc_out< bool > rp_ac_u[CFG_MEMU_RPORTS]
Definition: memu.h:1139
sc_signal< sc_uint< 32 > > snoop_adr
Definition: memu.h:1265
sc_signal< sc_uint< 20 > > tlb_adr_i
Definition: memu.h:1294
sc_in< sc_uint< 20 > > root_ppn
Definition: memu.h:1155
sc_signal< bool > gnt_rp_tagr[CFG_MEMU_RPORTS]
Definition: memu.h:1251
sc_signal< bool > tlb_ac_r_o
Definition: memu.h:1286
sc_signal< sc_uint< 32 > > wiadr_rp[CFG_MEMU_RPORTS]
Definition: memu.h:1264
sc_signal< SCacheTag > tagram_tag_out[TR_PORTS]
Definition: memu.h:1192
sc_signal< bool > tlb_ac_d_i
Definition: memu.h:1302
sc_signal< sc_uint< 2 > > master_bte[MASTER_NO]
Definition: memu.h:1206
sc_signal< bool > req_busif_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1255
sc_out< bool > wp_ack[CFG_MEMU_WPORTS]
Definition: memu.h:1144
sc_signal< sc_uint< 32 > > tagram_wadr[TR_PORTS]
Definition: memu.h:1191
sc_signal< SCacheTag > wp_tag_out[CFG_MEMU_WPORTS]
Definition: memu.h:1240
sc_signal< bool > gnt_wp_tagr_r[CFG_MEMU_WPORTS]
Definition: memu.h:1252
sc_signal< bool > busif_data_out_valid[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1219
sc_in< sc_uint< 4 > > rp_bsel[CFG_MEMU_RPORTS]
Definition: memu.h:1134
MBusController * busController
Definition: memu.h:1179
sc_signal< SCacheTag > rp_tag_in[CFG_MEMU_RPORTS]
Definition: memu.h:1231
sc_signal< bool > master_stb[MASTER_NO]
Definition: memu.h:1203
sc_signal< bool > req_rp_busif[CFG_MEMU_RPORTS]
Definition: memu.h:1260
sc_signal< sc_uint< 32 > > rp_busif_data_reg[CFG_MEMU_BUSIF_WIDTH/32]
Definition: memu.h:1227
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > master_dat[MASTER_NO]
Definition: memu.h:1209
sc_in< bool > tlb_flush
Definition: memu.h:1156
sc_out< sc_uint< 32 > > wb_adr_o
Definition: memu.h:1123
sc_signal< bool > req_busif_linelock
Definition: memu.h:1245
sc_signal< sc_uint< 32 > > rp_busif_data[CFG_MEMU_RPORTS]
Definition: memu.h:1228
sc_out< sc_uint< 2 > > wb_bte_o
Definition: memu.h:1121
sc_signal< bool > tlb_req
Definition: memu.h:1282
sc_signal< sc_uint< 32 > > tagram_adr[TR_PORTS]
Definition: memu.h:1190
sc_signal< bool > req_wp_bank[CFG_MEMU_WPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1255
sc_in< bool > wp_trap_no_u[CFG_MEMU_WPORTS]
Definition: memu.h:1151
sc_signal< bool > gnt_rp_busif[CFG_MEMU_RPORTS]
Definition: memu.h:1260
sc_signal< bool > bankram_wr[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1195
sc_in< bool > wp_paging[CFG_MEMU_WPORTS]
Definition: memu.h:1143
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > master_sel[MASTER_NO]
Definition: memu.h:1207
sc_signal< bool > busif_tag_rd
Definition: memu.h:1215
sc_signal< bool > tlb_ac_x_i
Definition: memu.h:1300
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_i
Definition: memu.h:1129
sc_signal< bool > req_wp_tagr[CFG_MEMU_WPORTS]
Definition: memu.h:1248
sc_signal< bool > tlb_hit
Definition: memu.h:1295
sc_signal< sc_uint< 4 > > busif_bsel
Definition: memu.h:1221
sc_signal< sc_uint< 32 > > ptw_phys_adr
Definition: memu.h:1269
sc_signal< bool > req_busif_tagw
Definition: memu.h:1248
sc_signal< bool > busif_bank_rd[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1215
void TransitionMethod()
Definition: memu.cpp:2989
sc_signal< SCacheTag > busif_tag_out
Definition: memu.h:1220
sc_in< bool > reset
Definition: memu.h:1114
sc_signal< sc_uint< 32 > > rp_way_out[CFG_MEMU_RPORTS]
Definition: memu.h:1232
sc_signal< bool > gnt_busif_tagw
Definition: memu.h:1250
sc_signal< bool > req_wp_busif[CFG_MEMU_WPORTS]
Definition: memu.h:1261
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > wb_sel_o
Definition: memu.h:1122
void InitSubmodules()
Definition: memu.cpp:2542
sc_signal< bool > busif_ac_x
Definition: memu.h:1222
sc_signal< bool > ptw_ac_w
Definition: memu.h:1275
sc_in< bool > wp_trap_u[CFG_MEMU_WPORTS]
Definition: memu.h:1151
sc_in< sc_uint< 32 > > rp_adr[CFG_MEMU_RPORTS]
Definition: memu.h:1137
sc_signal< bool > tlb_wr
Definition: memu.h:1282
sc_signal< bool > busif_paging
Definition: memu.h:1224
sc_signal< sc_uint< 32 > > busif_adr_in
Definition: memu.h:1217
sc_in< bool > clk
Definition: memu.h:1114
MTlb * tlb
Definition: memu.h:1182
sc_in< bool > wp_wr[CFG_MEMU_WPORTS]
Definition: memu.h:1141
sc_signal< bool > tlb_ac_w_i
Definition: memu.h:1299
sc_signal< bool > gnt_wp_linelock[CFG_MEMU_WPORTS]
Definition: memu.h:1246
sc_signal< bool > ptw_ac_r
Definition: memu.h:1274
void Trace(sc_trace_file *tf, int levels=1)
Definition: memu.cpp:2393
sc_signal< sc_uint< 32 > > rp_bank_sel[CFG_MEMU_RPORTS]
Definition: memu.h:1234
sc_signal< bool > req_wp_tagw[CFG_MEMU_WPORTS]
Definition: memu.h:1248
sc_out< bool > wp_ac_w[CFG_MEMU_WPORTS]
Definition: memu.h:1150
sc_in< bool > rp_paging[CFG_MEMU_RPORTS]
Definition: memu.h:1135
sc_signal< bool > gnt_busif_tagr_r
Definition: memu.h:1252
sc_signal< bool > busif_busy
Definition: memu.h:1214
sc_signal< bool > ptw_ac_x
Definition: memu.h:1276
MMemu(sc_module_name name)
Definition: memu.h:1160
sc_signal< bool > switch_master
Definition: memu.h:1210
sc_signal< bool > wp_bank_wr[CFG_MEMU_WPORTS]
Definition: memu.h:1239
sc_signal< sc_uint< 32 > > busif_adr_out
Definition: memu.h:1217
sc_signal< bool > gnt_wp_tagw_r[CFG_MEMU_WPORTS]
Definition: memu.h:1252
sc_signal< EBusIfOperation > rp_busif_op[CFG_MEMU_RPORTS]
Definition: memu.h:1229
sc_signal< bool > master_we[MASTER_NO]
Definition: memu.h:1204
sc_signal< bool > wp_busif_nolinelock[CFG_MEMU_WPORTS]
Definition: memu.h:1238
sc_signal< EBusIfOperation > busif_op
Definition: memu.h:1213
sc_in< sc_uint< 3 > > wp_cache_op[CFG_MEMU_WPORTS]
Definition: memu.h:1147
sc_signal< bool > req_busif_tagr
Definition: memu.h:1248
sc_signal< bool > ptw_req
Definition: memu.h:1271
sc_signal< bool > tlb_superpage_i
Definition: memu.h:1293
MPtw * ptw
Definition: memu.h:1181
sc_out< sc_uint< 32 > > rp_data[CFG_MEMU_RPORTS]
Definition: memu.h:1138
sc_signal< bool > gnt_busif_tagw_r
Definition: memu.h:1252
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat_o
Definition: memu.h:1124
sc_signal< bool > ptw_ack
Definition: memu.h:1272
sc_signal< bool > gnt_wp_busif[CFG_MEMU_WPORTS]
Definition: memu.h:1261
sc_out< bool > wb_stb_o
Definition: memu.h:1118
sc_signal< bool > tagram_rd[TR_PORTS]
Definition: memu.h:1189
sc_signal< bool > busif_tag_wr
Definition: memu.h:1215
sc_signal< bool > tlb_ac_r_i
Definition: memu.h:1298
sc_in< bool > wp_direct[CFG_MEMU_WPORTS]
Definition: memu.h:1141
sc_signal< bool > ptw_ac_u
Definition: memu.h:1277
sc_signal< bool > tlb_ac_a_i
Definition: memu.h:1303
void InterconnectMethod()
Definition: memu.cpp:2995
sc_signal< bool > tagram_ready
Definition: memu.h:1189
sc_signal< bool > tlb_ac_w_o
Definition: memu.h:1287
sc_signal< bool > wp_tag_wr[CFG_MEMU_WPORTS]
Definition: memu.h:1239
sc_signal< bool > tlb_miss
Definition: memu.h:1296
sc_signal< sc_uint< 32 > > adr_wp[CFG_MEMU_WPORTS]
Definition: memu.h:1264
sc_signal< bool > ptw_ac_a
Definition: memu.h:1279
sc_signal< bool > req_rp_bank[CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1256
sc_signal< bool > gnt_rp_bank[CFG_MEMU_RPORTS][CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1258
sc_signal< bool > busif_trap_u
Definition: memu.h:1223
sc_signal< bool > req_wp_linelock[CFG_MEMU_WPORTS]
Definition: memu.h:1245
sc_signal< bool > tlb_ac_u_i
Definition: memu.h:1301
sc_signal< bool > bankram_rd[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1195
sc_signal< bool > busif_ac_r
Definition: memu.h:1222
sc_out< sc_uint< 3 > > wb_cti_o
Definition: memu.h:1120
sc_signal< sc_uint< 32 > > ptw_virt_adr
Definition: memu.h:1270
sc_signal< sc_uint< 32 > > busif_data_out[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1218
~MMemu()
Definition: memu.h:1167
sc_signal< sc_uint< 32 > > bankram_rdata[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1199
sc_signal< sc_uint< 32 > > rp_bank_data_in[CFG_MEMU_RPORTS]
Definition: memu.h:1233
sc_out< bool > wb_cyc_o
Definition: memu.h:1117
sc_signal< bool > master_cyc[MASTER_NO]
Definition: memu.h:1202
sc_signal< bool > gnt_rp_tagr_r[CFG_MEMU_RPORTS]
Definition: memu.h:1253
sc_signal< sc_uint< 32 > > wiadr_busif
Definition: memu.h:1264
sc_signal< bool > wp_bank_rd[CFG_MEMU_WPORTS]
Definition: memu.h:1239
void InitInterconnectMethod()
Definition: memu.cpp:2942
sc_signal< bool > gnt_busif_linelock
Definition: memu.h:1246
sc_signal< sc_uint< 3 > > master_cti[MASTER_NO]
Definition: memu.h:1205
sc_signal< sc_uint< 4 > > bankram_wen[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1196
sc_signal< bool > busif_ac_u
Definition: memu.h:1222
sc_signal< bool > gnt_busif_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1257
MBusIf * busIf
Definition: memu.h:1180
sc_signal< sc_uint< 20 > > tlb_va_o
Definition: memu.h:1283
sc_in< sc_uint< 4 > > wp_bsel[CFG_MEMU_WPORTS]
Definition: memu.h:1142
sc_signal< sc_uint< 32 > > wp_bank_data_in[CFG_MEMU_WPORTS]
Definition: memu.h:1241
sc_signal< sc_uint< 32 > > busif_data_in[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1217
MBankRam * bankRam[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:1178
sc_in< bool > wp_lres_scond[CFG_MEMU_WPORTS]
Definition: memu.h:1145
sc_out< bool > rp_ac_r[CFG_MEMU_RPORTS]
Definition: memu.h:1139
MReadPort * readPorts[CFG_MEMU_RPORTS]
Definition: memu.h:1184
sc_signal< bool > gnt_wp_tagr[CFG_MEMU_WPORTS]
Definition: memu.h:1250
sc_signal< sc_uint< 32 > > way_wp[CFG_MEMU_WPORTS]
Definition: memu.h:1264
sc_out< bool > wp_scond_ok[CFG_MEMU_WPORTS]
Definition: memu.h:1146
sc_out< bool > wb_we_o
Definition: memu.h:1119
sc_signal< sc_uint< 32 > > bankram_wiadr[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1197
sc_out< bool > rp_ac_x[CFG_MEMU_RPORTS]
Definition: memu.h:1139
sc_signal< bool > ptw_ac_d
Definition: memu.h:1278
sc_signal< bool > tlb_superpage_o
Definition: memu.h:1285
sc_signal< sc_uint< 4 > > wp_bank_bsel[CFG_MEMU_WPORTS]
Definition: memu.h:1242
sc_signal< bool > tlb_ac_x_o
Definition: memu.h:1288
MWritePort * writePorts[CFG_MEMU_WPORTS]
Definition: memu.h:1185
sc_signal< bool > gnt_busif_tagr
Definition: memu.h:1250
sc_signal< sc_uint< 20 > > tlb_pa_o
Definition: memu.h:1284
void FreeSubmodules()
Definition: memu.cpp:2927
sc_signal< sc_uint< 32 > > bankram_wdata[CFG_MEMU_CACHE_BANKS][CFG_MEMU_BANK_RAM_PORTS]
Definition: memu.h:1198
MTagRam * tagRam
Definition: memu.h:1177
sc_signal< bool > snoop_stb[CFG_MEMU_WPORTS]
Definition: memu.h:1266
sc_signal< SCacheTag > busif_tag_in
Definition: memu.h:1220
sc_signal< bool > req_rp_tagr[CFG_MEMU_RPORTS]
Definition: memu.h:1249
sc_signal< bool > tlb_ac_d_o
Definition: memu.h:1290
sc_signal< bool > tlb_ac_a_o
Definition: memu.h:1291
sc_signal< SCacheTag > wp_tag_in[CFG_MEMU_WPORTS]
Definition: memu.h:1240
sc_signal< EBusIfOperation > wp_busif_op[CFG_MEMU_WPORTS]
Definition: memu.h:1237
sc_signal< bool > wp_tag_rd[CFG_MEMU_WPORTS]
Definition: memu.h:1239
sc_signal< sc_uint< 32 > > wp_bank_data_out[CFG_MEMU_WPORTS]
Definition: memu.h:1241
sc_signal< bool > gnt_wp_tagw[CFG_MEMU_WPORTS]
Definition: memu.h:1250
sc_in< bool > rp_rd[CFG_MEMU_RPORTS]
Definition: memu.h:1133
sc_signal< SCacheTag > tagram_tag_in[TR_PORTS]
Definition: memu.h:1192
sc_signal< bool > rp_bank_rd[CFG_MEMU_RPORTS]
Definition: memu.h:1230
sc_signal< bool > busif_nolinelock
Definition: memu.h:1214
sc_in< sc_uint< 32 > > wp_data[CFG_MEMU_WPORTS]
Definition: memu.h:1149
sc_signal< sc_uint< 32 > > master_adr[MASTER_NO]
Definition: memu.h:1208
Definition: memu.h:624
sc_out< bool > tag_rd
Definition: memu.h:660
sc_out< EBusIfOperation > busif_op
Definition: memu.h:652
sc_out< bool > port_ac_u
Definition: memu.h:643
sc_signal< EReadportState > state_reg
Definition: memu.h:708
sc_in< sc_uint< 32 > > snoop_adr
Definition: memu.h:671
sc_in< bool > port_direct
Definition: memu.h:637
sc_signal< bool > next_ac_r_reg
Definition: memu.h:726
sc_signal< sc_uint< 32 > > bank_sel_reg
Definition: memu.h:711
sc_out< bool > req_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:667
sc_signal< bool > next_ac_u_reg
Definition: memu.h:728
sc_signal< bool > ac_u_reg
Definition: memu.h:717
sc_in< bool > port_lres_scond
Definition: memu.h:645
sc_in< bool > gnt_tagr
Definition: memu.h:668
sc_signal< bool > next_ac_x_reg
Definition: memu.h:727
sc_out< sc_uint< 32 > > bank_sel
Definition: memu.h:662
sc_in< bool > busif_ac_x
Definition: memu.h:655
void Trace(sc_trace_file *tf, int level=1)
Definition: memu.cpp:1157
sc_signal< EReadportState > next_state
Definition: memu.h:722
sc_out< bool > req_busif
Definition: memu.h:667
sc_out< bool > req_tagr
Definition: memu.h:667
sc_in< bool > snoop_stb
Definition: memu.h:672
sc_in< sc_uint< 32 > > bank_data_in
Definition: memu.h:661
sc_out< sc_uint< 32 > > way_out
Definition: memu.h:664
sc_signal< bool > link_valid_reg
Definition: memu.h:714
sc_signal< bool > busif_hit
Definition: memu.h:721
void TransitionMethod()
Definition: memu.cpp:1227
sc_in< sc_uint< 32 > > busif_data
Definition: memu.h:650
sc_signal< bool > ac_r_reg
Definition: memu.h:715
sc_in< sc_uint< 32 > > busif_adr
Definition: memu.h:649
void HitMethod()
Definition: memu.cpp:1214
sc_in< bool > clk
Definition: memu.h:627
sc_out< sc_uint< 32 > > port_data
Definition: memu.h:640
sc_signal< bool > ac_x_reg
Definition: memu.h:716
sc_in< sc_uint< 32 > > port_adr
Definition: memu.h:639
sc_signal< bool > next_link_valid_reg
Definition: memu.h:725
sc_in< bool > reset
Definition: memu.h:627
sc_in< bool > busif_ac_u
Definition: memu.h:656
sc_in< bool > gnt_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:668
sc_in< bool > busif_ac_r
Definition: memu.h:654
void MainMethod()
Definition: memu.cpp:1243
sc_out< bool > bank_rd
Definition: memu.h:660
sc_signal< sc_uint< 32 > > link_adr_reg
Definition: memu.h:713
sc_in< bool > busif_data_valid[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:651
sc_in< SCacheTag > tag_in
Definition: memu.h:663
sc_signal< sc_uint< 32 > > next_bank_sel
Definition: memu.h:723
sc_signal< sc_uint< 32 > > next_link_adr_reg
Definition: memu.h:724
sc_out< bool > port_scond_ok
Definition: memu.h:646
MReadPort(sc_module_name name)
Definition: memu.h:676
sc_out< bool > port_ac_x
Definition: memu.h:642
sc_in< bool > gnt_busif
Definition: memu.h:668
sc_signal< int > state_trace
Definition: memu.h:709
sc_out< bool > port_ac_r
Definition: memu.h:641
sc_in< bool > busif_busy
Definition: memu.h:653
sc_out< bool > port_ack
Definition: memu.h:638
sc_in< bool > port_rd
Definition: memu.h:637
Definition: memu.h:263
sc_in< bool > reset
Definition: memu.h:266
sc_signal< bool > write_tag
Definition: memu.h:298
sc_signal< sc_uint< 6 > > use_iadr_reg[TR_PORTS+1]
Definition: memu.h:303
void Trace(sc_trace_file *tf, int level=1)
Definition: memu.cpp:241
sc_in< bool > wr[TR_PORTS]
Definition: memu.h:270
sc_in< SCacheTag > tag_in[TR_PORTS]
Definition: memu.h:275
sc_signal< sc_uint< CFG_MEMU_CACHE_WAYS_LD > > wtag_way
Definition: memu.h:299
sc_in< sc_uint< 32 > > adr[TR_PORTS]
Definition: memu.h:273
sc_signal< sc_uint< 8 > > counter
Definition: memu.h:306
void MainThread()
Definition: memu.cpp:304
sc_signal< sc_uint< 32 > > wtag_port
Definition: memu.h:301
sc_out< bool > ready
Definition: memu.h:267
sc_signal< sc_uint< 32 > > wtag_iadr
Definition: memu.h:300
sc_in< bool > rd_way
Definition: memu.h:271
STagEntry ram_[CFG_MEMU_CACHE_SETS]
Definition: memu.h:295
sc_in< bool > clk
Definition: memu.h:266
sc_in< bool > rd[TR_PORTS]
Definition: memu.h:269
sc_signal< sc_uint< 6 > > use_reg[TR_PORTS+1]
Definition: memu.h:303
sc_in< sc_uint< 32 > > wadr[TR_PORTS]
Definition: memu.h:274
MTagRam(sc_module_name name)
Definition: memu.h:281
sc_signal< bool > use_wr_reg[TR_PORTS+1]
Definition: memu.h:304
sc_out< SCacheTag > tag_out[TR_PORTS]
Definition: memu.h:277
Definition: tlb.h:139
Definition: memu.h:755
sc_in< sc_uint< 32 > > bank_data_in
Definition: memu.h:793
sc_in< bool > busif_ac_w
Definition: memu.h:788
sc_out< bool > busif_nolinelock
Definition: memu.h:786
sc_signal< sc_uint< 32 > > next_data_reg
Definition: memu.h:839
sc_in< bool > gnt_busif
Definition: memu.h:801
sc_in< bool > port_scond_ok
Definition: memu.h:780
sc_out< bool > tag_wr
Definition: memu.h:792
void Trace(sc_trace_file *tf, int level=1)
Definition: memu.cpp:1458
sc_in< bool > port_wr
Definition: memu.h:767
sc_signal< EWritePortState > next_state
Definition: memu.h:837
void TransitionMethod()
Definition: memu.cpp:1523
sc_in< bool > reset
Definition: memu.h:758
sc_out< bool > bank_rd
Definition: memu.h:792
sc_out< bool > bank_wr
Definition: memu.h:792
sc_in< bool > port_trap_u
Definition: memu.h:771
sc_out< bool > tag_rd
Definition: memu.h:792
sc_in< bool > port_lres_scond
Definition: memu.h:779
sc_out< bool > req_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:800
sc_in< bool > port_trap_no_u
Definition: memu.h:772
sc_signal< EWritePortState > state_reg
Definition: memu.h:830
sc_in< sc_uint< 3 > > port_cache_op
Definition: memu.h:774
sc_in< bool > gnt_bank[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:801
sc_in< bool > gnt_linelock
Definition: memu.h:801
sc_out< bool > req_tagr
Definition: memu.h:800
void MainMethod()
Definition: memu.cpp:1557
sc_out< SCacheTag > tag_out
Definition: memu.h:797
sc_out< sc_uint< 32 > > bank_data_out
Definition: memu.h:794
sc_signal< sc_uint< 32 > > data_reg
Definition: memu.h:834
sc_out< bool > req_linelock
Definition: memu.h:800
sc_in< sc_uint< 32 > > port_adr
Definition: memu.h:776
sc_in< sc_uint< 4 > > port_bsel
Definition: memu.h:768
sc_out< bool > req_tagw
Definition: memu.h:800
sc_out< bool > port_ac_w
Definition: memu.h:770
sc_in< bool > busif_busy
Definition: memu.h:787
sc_out< EBusIfOperation > busif_op
Definition: memu.h:785
sc_in< bool > gnt_tagw
Definition: memu.h:801
sc_in< sc_uint< 32 > > port_data
Definition: memu.h:777
sc_in< SCacheTag > tag_in
Definition: memu.h:796
sc_signal< SCacheTag > tag_reg
Definition: memu.h:833
sc_signal< int > state_trace
Definition: memu.h:831
sc_out< sc_uint< 4 > > bank_bsel
Definition: memu.h:795
sc_in< bool > gnt_tagr
Definition: memu.h:801
sc_in< sc_uint< 32 > > busif_adr
Definition: memu.h:784
sc_out< bool > port_ack
Definition: memu.h:769
sc_in< bool > port_direct
Definition: memu.h:767
sc_out< bool > req_busif
Definition: memu.h:800
sc_in< bool > clk
Definition: memu.h:758
sc_signal< SCacheTag > next_tag_reg
Definition: memu.h:838
MWritePort(sc_module_name name)
Definition: memu.h:805
#define CFG_NUT_CPU_CORES
Number of cores overall (derived).
Definition: paranut-config.h:98
#define CFG_NUT_CPU_CORES_LD
Number of cores overall as log2.
Definition: paranut-config.h:96
#define CFG_MEMU_RPORTS
Number of read ports (RPORTS) in the MemU (derived).
Definition: paranut-config.h:236
#define CFG_MEMU_CACHE_WAYS
Number of cache ways (derived).
Definition: paranut-config.h:203
#define CFG_MEMU_BANK_RAM_PORTS
Number of ports per bank.
Definition: paranut-config.h:210
#define CFG_MEMU_WPORTS
Number of write ports (WPORTS) in the MemU (derived).
Definition: paranut-config.h:234
#define CFG_MEMU_CACHE_WAYS_LD
Number of cache ways as log2.
Definition: paranut-config.h:201
#define CFG_MEMU_CACHE_BANKS
Number of cache banks (derived).
Definition: paranut-config.h:186
#define CFG_MEMU_BUSIF_WIDTH
Busif Data Width.
Definition: paranut-config.h:228
#define CFG_MEMU_CACHE_SETS_LD
Number of cache sets as log2.
Definition: paranut-config.h:191
#define CFG_MEMU_CACHE_BANKS_LD
Number of cache banks as log2.
Definition: paranut-config.h:184
#define CFG_MEMU_CACHE_SETS
Number of cache sets (derived).
Definition: paranut-config.h:193
#define PN_TRACE(TF, OBJ)
Add sc_object OBJ to the trace file TF.
Definition: base.h:207
#define PN_TRACE_R(TF, OBJ, MEMBER, STR)
Helper macro for recursively calling sc_trace in own types/structs.
Definition: base.h:255
#define NUM_BITS(A)
Number of bits necessary to encode A.
Definition: base.h:156
#define MAX(A, B)
Maximum of A and B.
Definition: base.h:154
EWritePortState
Definition: memu.h:734
@ s_wp_recheck
Definition: memu.h:744
@ s_wp_replace_wait_busif
Definition: memu.h:747
@ s_wp_special_request_busif_only
Definition: memu.h:748
@ s_wp_recheck_read_tag
Definition: memu.h:745
@ s_wp_write_bank
Definition: memu.h:741
@ s_wp_request_linelock_only
Definition: memu.h:737
@ s_wp_miss
Definition: memu.h:742
@ s_wp_special
Definition: memu.h:749
@ s_wp_write_tag1
Definition: memu.h:740
@ s_wp_read_tag
Definition: memu.h:738
@ s_wp_request_busif_only
Definition: memu.h:743
@ s_wp_write_tag1_and_bank
Definition: memu.h:739
@ s_wp_direct
Definition: memu.h:736
@ s_wp_replace
Definition: memu.h:746
@ s_wp_page_fault
Definition: memu.h:751
@ s_wp_special_wait_complete
Definition: memu.h:750
@ s_wp_init
Definition: memu.h:735
EReadportState
Definition: memu.h:611
@ s_rp_request_tag_only
Definition: memu.h:614
@ s_rp_read_tag
Definition: memu.h:615
@ s_rp_init
Definition: memu.h:612
@ s_rp_miss_wait_busif
Definition: memu.h:617
@ s_rp_miss_replace
Definition: memu.h:620
@ s_rp_miss_read_tag
Definition: memu.h:619
@ s_rp_direct_wait_busif
Definition: memu.h:613
@ s_rp_read_bank
Definition: memu.h:616
@ s_rp_miss_request_tag
Definition: memu.h:618
EBusIfMmuState
Definition: memu.h:409
@ BifMmuAwaitResponse
Definition: memu.h:412
@ BifMmuReq
Definition: memu.h:411
@ BifMmuPteSuccess
Definition: memu.h:414
@ BifMmuIdle
Definition: memu.h:410
@ BifMmuDone
Definition: memu.h:415
@ BifMmuLoadPageEntry
Definition: memu.h:413
sc_uint< 4 > EBusIfOperation
Definition: memu.h:430
#define BUSIF_DATA_REG_NUM
Definition: memu.h:443
EBusIfState
Definition: memu.h:390
@ BifCacheRequestLLWait
Definition: memu.h:395
@ BifCacheAll
Definition: memu.h:405
@ BifDirectWrite
Definition: memu.h:394
@ BifCacheRequestRTWait
Definition: memu.h:396
@ BifDirectRead1
Definition: memu.h:392
@ BifCacheFillIdataPageFault
Definition: memu.h:406
@ BifCacheReadTag
Definition: memu.h:397
@ BifIdle
Definition: memu.h:391
@ BifCacheWriteBackVictim
Definition: memu.h:403
@ BifDirectRead2
Definition: memu.h:393
@ BifCacheReadDirtyBanks
Definition: memu.h:399
@ BifCacheReplaceInvalidateTag
Definition: memu.h:400
@ BifCacheReplaceReadIdata
Definition: memu.h:398
@ BifCacheReplaceWriteBanks
Definition: memu.h:401
@ BifCacheAck
Definition: memu.h:404
@ BifCacheWriteTag
Definition: memu.h:402
#define TR_PORTS
Definition: memu.h:235
#define MASTER_NO
Definition: memu.h:61
Configuration Makros used in most ParaNut files.
Definition: memu.h:125
MSelector(const sc_module_name &name, sc_uint< 32 > FAST_INDEX=0)
Definition: memu.h:175
sc_in< sc_uint< MAX(1, CFG_NUT_CPU_CORES_LD)> > prio
Definition: memu.h:131
sc_in< bool > reset
Definition: memu.h:128
sc_out< SSelectorIO< DWIDTH, SEL_MAX > > out
Definition: memu.h:130
sc_in< bool > clk
Definition: memu.h:128
void Trace(sc_trace_file *tf, int level)
Definition: memu.h:186
sc_in< SSelectorIO< DWIDTH, SEL_MAX > > f_in
Definition: memu.h:129
sc_in< SSelectorIO< DWIDTH, SEL_MAX > > s_in
Definition: memu.h:129
void TransitionMethod()
Definition: memu.h:133
void CombMethod()
Definition: memu.h:141
Definition: memu.h:99
void Trace(sc_trace_file *tf, int level)
Definition: memu.h:118
sc_out< SSelectorIO< DWIDTH, SEL_MAX > > out
Definition: memu.h:103
sc_in< SSelectorIO< DWIDTH, SEL_MAX > > f_in
Definition: memu.h:102
void CombMethod()
Definition: memu.h:105
MSelectorPass(const sc_module_name &name)
Definition: memu.h:110
Definition: memu.h:480
bool ac_w
Definition: memu.h:485
friend void sc_trace(sc_trace_file *tf, const SBusIfMmuRegs &t, const std::string &name)
Definition: memu.cpp:112
bool ac_r
Definition: memu.h:484
bool operator==(const SBusIfMmuRegs &t)
bool ack
Definition: memu.h:483
friend ostream & operator<<(ostream &o, const SBusIfMmuRegs &t)
sc_uint< 32 > adr
Definition: memu.h:482
bool ac_u
Definition: memu.h:487
EBusIfMmuState state
Definition: memu.h:481
bool ac_x
Definition: memu.h:486
bool ac_d
Definition: memu.h:488
bool ac_a
Definition: memu.h:489
Definition: memu.h:446
SCacheTag tag
Definition: memu.h:460
EBusIfState state
Definition: memu.h:447
bool operator==(const SBusIfRegs &t)
Definition: memu.cpp:68
sc_uint< CFG_MEMU_BUSIF_WIDTH > idata[BUSIF_DATA_REG_NUM]
Definition: memu.h:455
sc_uint< 32 > phys_adr
Definition: memu.h:451
sc_uint< CFG_MEMU_CACHE_BANKS_LD > adr_ofs
Definition: memu.h:453
sc_uint< 32 > odata[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:456
bool ac_x
Definition: memu.h:465
sc_uint< CFG_MEMU_CACHE_BANKS > last_banks_left
Definition: memu.h:459
EBusIfOperation op
Definition: memu.h:448
sc_uint< 32 > virt_adr
Definition: memu.h:452
bool transl_done
Definition: memu.h:467
bool linelock
Definition: memu.h:449
bool paging_en
Definition: memu.h:468
sc_uint< BUSIF_DATA_REG_NUM_LD > cnt
Definition: memu.h:457
friend void sc_trace(sc_trace_file *tf, const SBusIfRegs &t, const std::string &name)
Definition: memu.cpp:82
bool idata_valid[CFG_MEMU_CACHE_BANKS]
Definition: memu.h:454
sc_uint< CFG_MEMU_CACHE_BANKS > banks_left
Definition: memu.h:458
sc_uint< 4 > bsel
Definition: memu.h:450
friend ostream & operator<<(ostream &o, const SBusIfRegs &t)
bool ac_w
Definition: memu.h:464
bool ac_u
Definition: memu.h:466
bool ac_r
Definition: memu.h:463
Definition: memu.h:207
bool ac_x
Definition: memu.h:209
bool ac_r
Definition: memu.h:209
friend ostream & operator<<(ostream &os, const SCacheTag &t)
Definition: memu.cpp:46
sc_uint< 32-CFG_MEMU_CACHE_SETS_LD-CFG_MEMU_CACHE_BANKS_LD-2 > tadr
Definition: memu.h:210
friend void sc_trace(sc_trace_file *tf, const SCacheTag &t, const std::string &name)
Definition: memu.cpp:53
bool valid
Definition: memu.h:208
bool ac_w
Definition: memu.h:209
bool ac_u
Definition: memu.h:209
sc_uint< CFG_MEMU_CACHE_WAYS_LD > way
Definition: memu.h:211
bool operator==(const SCacheTag &t) const
Definition: memu.cpp:41
bool dirty
Definition: memu.h:208
Definition: memu.h:73
friend ostream & operator<<(ostream &o, const SSelectorIO &t)
Definition: memu.h:86
bool sel_valid
Definition: memu.h:76
sc_uint< DWIDTH > dat
Definition: memu.h:74
bool operator==(const SSelectorIO &t)
Definition: memu.h:82
SSelectorIO(sc_uint< DWIDTH > _dat=0, sc_uint< NUM_BITS(SEL_MAX)> _sel=0, bool _sel_valid=0)
Definition: memu.h:78
friend void sc_trace(sc_trace_file *tf, const SSelectorIO &t, const std::string &name)
Definition: memu.h:91
sc_uint< NUM_BITS(SEL_MAX)> sel
Definition: memu.h:75
Definition: memu.h:247
STag tag[CFG_MEMU_CACHE_WAYS]
Definition: memu.h:248
sc_uint< 6 > use
Definition: memu.h:249
Definition: memu.h:239
bool ac_x
Definition: memu.h:241
bool ac_w
Definition: memu.h:241
bool valid
Definition: memu.h:240
bool dirty
Definition: memu.h:240
bool ac_u
Definition: memu.h:241
sc_uint< 32-CFG_MEMU_CACHE_SETS_LD-CFG_MEMU_CACHE_BANKS_LD-2 > tadr
Definition: memu.h:242
bool ac_r
Definition: memu.h:241
sc_trace_file * tf
Definition: tlb_tb.cpp:94