47 #if CFG_EXU_PERFCOUNT_ENABLE == 1
48 #define CYCLEREG_LOW (csr_mcycle.read () (31, 0))
49 #define CYCLEREG_HIGH (csr_mcycle.read () (63, 32))
50 #define PERFREGS(COUNTER) csr_mhpmcounter[COUNTER].read ()
52 #define PERFREGS(COUNTER) sc_uint<CFG_EXU_PERFCOUNTER_BITS> (0x0)
53 #define CYCLEREG_LOW 0x0
54 #define CYCLEREG_HIGH 0x0
248 sc_in<sc_uint<32> > pc, ir;
249 sc_in<bool> exu_pop_priv_ir_stack_dreg;
251 sc_in<sc_uint<EX_ID_LENGTH> > ex_id_reg;
252 sc_in<bool> exception;
253 sc_in<bool> irq_dreg;
255 sc_out<bool> mtie_out;
261 sc_in<sc_uint<CFG_NUT_CPU_CORES_LD> > hartID;
263 sc_in<bool> cpu_enabled, linked;
264 sc_in<bool> csr_enable;
265 sc_in<sc_uint<5> > exu_cause;
267 sc_in<bool> exu_dbg, exu_dbg_reg, exu_dbg_req, exu_dbg_enter_dreg;
270 sc_out<bool> exu_delegate_dreg;
271 sc_in<bool> sret_dreg;
273 sc_out<bool> exu_csr_exception;
282 exu_csr_dcsr_ebreakm;
283 sc_out<bool> exu_isHalted;
285 sc_out<sc_uint<2> > exu_load_store_priv_mode;
299 sc_out<bool> exu_ifu_paging_mode;
300 sc_out<bool> exu_lsu_paging_mode;
301 sc_out<sc_uint<20> > exu_csr_satp_root_ppn;
303 sc_out<sc_uint<CFG_NUT_CPU_CORES> > exu_m3_pnce;
304 sc_out<sc_uint<CFG_NUT_CPU_CORES> > exu_m3_pnlm;
305 sc_out<sc_uint<CFG_NUT_CPU_CORES> > exu_m3_pnxsel;
306 sc_in<sc_uint<2> > exu_m3_priv_mode;
309 sc_out<bool> exu_cache_flush;
313 sc_out<bool> exu_m3_icache_enable, exu_m3_dcache_enable;
315 sc_in<sc_uint<32> > csr_tval;
316 sc_in<sc_uint<CFG_NUT_CPU_CORES> > m3_pnhaltreq;
318 sc_in<sc_uint<3> > csr_function_reg;
319 sc_in<sc_uint<5> > csr_rs1_reg;
320 sc_in<sc_uint<12> > csr_adr_reg;
321 sc_in<sc_uint<32> > csr_op_a;
322 sc_out<sc_uint<32> > exu_csr_rdata;
324 sc_out<sc_uint<2> > exu_priv_mode;
327 sc_in<sc_uint<CFG_NUT_CPU_CORES> > m3_pnx;
329 #if CFG_EXU_PERFCOUNT_ENABLE == 1
330 sc_in<bool> perf_inc;
331 sc_in<sc_uint<CFG_EXU_PERFCOUNTERS_LD> > perf_addr;
335 void Trace (sc_trace_file *
tf,
int levels = 1);
338 void CSRHandleMethod ();
339 void CSRReadMethod ();
340 void CSRWriteMethod ();
341 void OutputMethod ();
344 void setMstatus (sc_uint<32> wdata);
345 sc_uint<32> getMstatus ();
346 void setSstatus (sc_uint<32> wdata);
347 sc_uint<32> getSstatus ();
350 SC_METHOD (CSRHandleMethod);
351 sensitive << csr_enable << csr_function_reg << csr_op_a << csr_rs1_reg
352 << csr_rdata << csr_rd_exception << csr_adr_reg
354 SC_METHOD (CSRReadMethod);
355 sensitive << csr_adr_reg << csr_enable << csr_mepc << csr_mcause << csr_mtval
356 << csr_mtvec << csr_mscratch << csr_mstatus_MIE << csr_mstatus_MPIE
357 << exu_cause << m3_pnx << hartID << inCePU << cpu_enabled
358 << linked << csr_pncache << csr_mstatus_MPRV << csr_mstatus_MPP;
360 sensitive << csr_pnce[i] << csr_pnece[i] << csr_pnlm[i] << csr_pnxsel[i] << csr_pnx[i];
361 #if CFG_NUT_CPU_GROUPS
362 sensitive << csr_pngrpsel;
364 SC_METHOD (CSRWriteMethod);
365 sensitive <<
clk.pos ();
366 SC_METHOD (OutputMethod);
367 sensitive << csr_exception << csr_rd_exception << exu_cache_flush_reg
368 << csr_mstatus_MIE << exu_csr_mstatus_SUM << csr_mstatus_TSR << csr_mstatus_TVM << csr_mstatus_SIE
369 << csr_mtvec << priv_mode_reg << csr_satp_root_ppn << csr_satp_mode
370 << csr_sepc << csr_stvec << csr_mideleg << delegate_dreg << csr_pncache
371 << csr_dcsr_step << csr_dcsr_ebreakm << csr_mcause << csr_rdata << csr_mepc << csr_dpc
372 << csr_mie_MTIE << csr_mstatus_MPP << csr_mstatus_MPRV;
374 sensitive << csr_pnce[i] << csr_pnece[i] << csr_pnlm[i] << csr_pnx[i] << csr_pnxsel[i];
377 #if CFG_EXU_PERFCOUNT_ENABLE == 1
378 SC_METHOD (PerfcountMethod);
379 sensitive <<
clk.pos ();
384 sc_signal<sc_uint<32> >
393 sc_signal<sc_uint<2> > priv_mode_reg, next_priv_mode_reg;
396 sc_signal<bool> delegate_dreg;
397 sc_signal<bool> exu_cache_flush_reg;
403 sc_signal<sc_uint<3> > csr_dcsr_cause;
404 sc_signal<sc_uint<2> > csr_dcsr_prv;
425 sc_signal<sc_uint<2> >
429 sc_signal<bool> csr_satp_mode;
430 sc_signal<sc_uint<20> > csr_satp_root_ppn;
432 sc_signal<sc_uint<32> >
458 #if CFG_NUT_CPU_GROUPS > 0
460 sc_signal<sc_uint<CFG_NUT_CPU_GROUPS> > csr_pngrpsel;
463 static const bool csr_pngrpsel = 0x0;
465 sc_signal<sc_uint<2> > csr_pncache;
467 #if CFG_EXU_PERFCOUNT_ENABLE == 1
469 void PerfcountMethod ();
471 sc_signal<sc_uint<64> > csr_mcycle;
Helpers, Makros and performance measuring Classes used in most ParaNut files.
@ uhpmcounter17h
Definition: csr.h:193
@ uhpmcounter31
Definition: csr.h:175
@ ucause
Definition: csr.h:139
@ uhpmcounter8
Definition: csr.h:152
@ mip
Definition: csr.h:84
@ mimpid
Definition: csr.h:68
@ uhpmcounter22
Definition: csr.h:166
@ uip
Definition: csr.h:141
@ uhpmcounter5h
Definition: csr.h:181
@ uhpmcounter11
Definition: csr.h:155
@ uhpmcounter24
Definition: csr.h:168
@ utval
Definition: csr.h:140
@ uhpmcounter29h
Definition: csr.h:205
@ utime
Definition: csr.h:145
@ sedeleg
Definition: csr.h:115
@ sideleg
Definition: csr.h:116
@ pngrpsel
Definition: csr.h:219
@ uhpmcounter28h
Definition: csr.h:204
@ uhpmcounter5
Definition: csr.h:149
@ pnmemsize
Definition: csr.h:230
@ uhpmcounter6h
Definition: csr.h:182
@ uhpmcounter6
Definition: csr.h:150
@ pnclockinfo
Definition: csr.h:229
@ uhpmcounter8h
Definition: csr.h:184
@ uhpmcounter20h
Definition: csr.h:196
@ sie
Definition: csr.h:117
@ mstatus
Definition: csr.h:72
@ mcycle
Definition: csr.h:87
@ pnlm
Definition: csr.h:221
@ uhpmcounter24h
Definition: csr.h:200
@ pncachesets
Definition: csr.h:228
@ pnepc
Definition: csr.h:239
@ mhpmcounter4
Definition: csr.h:90
@ dpc
Definition: csr.h:211
@ satp
Definition: csr.h:129
@ mhpmevent3
Definition: csr.h:109
@ stval
Definition: csr.h:125
@ mhpmcounter4h
Definition: csr.h:100
@ uhpmcounter25h
Definition: csr.h:201
@ mhpmcounter6h
Definition: csr.h:102
@ ustatus
Definition: csr.h:132
@ mhpmcounter7h
Definition: csr.h:103
@ mhpmcounter8
Definition: csr.h:94
@ sstatus
Definition: csr.h:114
@ uhpmcounter18h
Definition: csr.h:194
@ uhpmcounter27h
Definition: csr.h:203
@ pncpus
Definition: csr.h:235
@ uhpmcounter12h
Definition: csr.h:188
@ uhpmcounter25
Definition: csr.h:169
@ uhpmcounter9
Definition: csr.h:153
@ uhpmcounter21h
Definition: csr.h:197
@ mcycleh
Definition: csr.h:97
@ mhpmcounter7
Definition: csr.h:93
@ mhpmcounter8h
Definition: csr.h:104
@ uhpmcounter7h
Definition: csr.h:183
@ uhpmcounter13
Definition: csr.h:157
@ mtval
Definition: csr.h:83
@ pnx
Definition: csr.h:226
@ dscratch0
Definition: csr.h:212
@ mhpmevent31
Definition: csr.h:111
@ uhpmcounter12
Definition: csr.h:156
@ pnxsel
Definition: csr.h:222
@ uhpmcounter30
Definition: csr.h:174
@ uinstret
Definition: csr.h:146
@ pncache
Definition: csr.h:216
@ uhpmcounter19
Definition: csr.h:163
@ uhpmcounter22h
Definition: csr.h:198
@ mhpmcounter31h
Definition: csr.h:106
@ uhpmcounter31h
Definition: csr.h:207
@ minstreth
Definition: csr.h:98
@ scounteren
Definition: csr.h:119
@ stvec
Definition: csr.h:118
@ uhpmcounter3
Definition: csr.h:147
@ uhpmcounter17
Definition: csr.h:161
@ uhpmcounter18
Definition: csr.h:162
@ misa
Definition: csr.h:73
@ uhpmcounter27
Definition: csr.h:171
@ uhpmcounter15
Definition: csr.h:159
@ utvec
Definition: csr.h:134
@ uie
Definition: csr.h:133
@ pncoreid
Definition: csr.h:236
@ mtvec
Definition: csr.h:77
@ uhpmcounter20
Definition: csr.h:164
@ mhpmcounter3h
Definition: csr.h:99
@ uhpmcounter26h
Definition: csr.h:202
@ mhpmcounter5
Definition: csr.h:91
@ uhpmcounter4h
Definition: csr.h:180
@ mvendorid
Definition: csr.h:66
@ pncause
Definition: csr.h:240
@ scause
Definition: csr.h:124
@ pntimebase
Definition: csr.h:232
@ ucycleh
Definition: csr.h:176
@ uhpmcounter3h
Definition: csr.h:179
@ uhpmcounter10
Definition: csr.h:154
@ pncacheinfo
Definition: csr.h:227
@ uhpmcounter16
Definition: csr.h:160
@ uhpmcounter13h
Definition: csr.h:189
@ medeleg
Definition: csr.h:74
@ minstret
Definition: csr.h:88
@ mhpmcounter3
Definition: csr.h:89
@ uhpmcounter29
Definition: csr.h:173
@ uhpmcounter30h
Definition: csr.h:206
@ tselect
Definition: csr.h:213
@ marchid
Definition: csr.h:67
@ mepc
Definition: csr.h:81
@ uhpmcounter7
Definition: csr.h:151
@ uhpmcounter21
Definition: csr.h:165
@ mhpmcounter6
Definition: csr.h:92
@ mscratch
Definition: csr.h:80
@ uhpmcounter15h
Definition: csr.h:191
@ mhpmcounter31
Definition: csr.h:96
@ uhpmcounter14h
Definition: csr.h:190
@ dcsr
Definition: csr.h:210
@ ucycle
Definition: csr.h:144
@ uscratch
Definition: csr.h:137
@ uinstreth
Definition: csr.h:178
@ uepc
Definition: csr.h:138
@ uhpmcounter9h
Definition: csr.h:185
@ uhpmcounter4
Definition: csr.h:148
@ mhpmcounter5h
Definition: csr.h:101
@ sepc
Definition: csr.h:123
@ sip
Definition: csr.h:126
@ uhpmcounter23h
Definition: csr.h:199
@ uhpmcounter26
Definition: csr.h:170
@ uhpmcounter28
Definition: csr.h:172
@ uhpmcounter16h
Definition: csr.h:192
@ uhpmcounter11h
Definition: csr.h:187
@ uhpmcounter10h
Definition: csr.h:186
@ uhpmcounter14
Definition: csr.h:158
@ uhpmcounter23
Definition: csr.h:167
@ mideleg
Definition: csr.h:75
@ mie
Definition: csr.h:76
@ mcause
Definition: csr.h:82
@ utimeh
Definition: csr.h:177
@ pnece
Definition: csr.h:231
@ uhpmcounter19h
Definition: csr.h:195
@ sscratch
Definition: csr.h:122
@ pnm2cp
Definition: csr.h:225
@ pnce
Definition: csr.h:220
@ mhartid
Definition: csr.h:69
ECSRFunc
Definition: csr.h:57
@ CSRRC
Definition: csr.h:60
@ CSRRS
Definition: csr.h:59
@ CSRRW
Definition: csr.h:58
sc_signal< bool > reset
Definition: dm_tb.cpp:54
sc_signal< bool > clk
Definition: dm_tb.cpp:54
#define CFG_EXU_PERFCOUNTERS
Performance counter number of registers (derived).
Definition: paranut-config.h:169
#define CFG_NUT_CPU_CORES
Number of cores overall (derived).
Definition: paranut-config.h:98
#define CFG_NUT_CPU_GROUPS
Number of cpu groups (derived).
Definition: paranut-config.h:100
#define XLEN
Number of instruction/register Bits.
Definition: base.h:164
#define MIN(A, B)
Minimum of A and B.
Definition: base.h:152
Configuration Makros used in most ParaNut files.
The MPeripheral class containing the interface for Wishbone slave peripherals.
sc_trace_file * tf
Definition: tlb_tb.cpp:94