ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
nut.h
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1 /*************************************************************************
2 
3  This file is part of the ParaNut project.
4 
5  Copyright (C) 2010-2022 Alexander Bahle <alexander.bahle@hs-augsburg.de>
6  Gundolf Kiefer <gundolf.kiefer@hs-augsburg.de>
7  Christian H. Meyer <christian.meyer@hs-augsburg.de>
8  Nico Borgsmüller <nico.borgsmueller@hs-augsburg.d
9  Hochschule Augsburg, University of Applied Sciences
10 
11  Description:
12  This is the top-level component of the ParaNut.
13  It contains the following sub-modules:
14  - 1 memory unit (MEMU)
15  for each CPU:
16  - 1 instruction fetch unit (IFU)
17  - 1 execution unit (EXU)
18  - 1 load-store unit (LSU)
19 
20  Redistribution and use in source and binary forms, with or without modification,
21  are permitted provided that the following conditions are met:
22 
23  1. Redistributions of source code must retain the above copyright notice, this
24  list of conditions and the following disclaimer.
25 
26  2. Redistributions in binary form must reproduce the above copyright notice,
27  this list of conditions and the following disclaimer in the documentation and/or
28  other materials provided with the distribution.
29 
30  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
34  ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
37  ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 
41  *************************************************************************/
42 
43 
44 #ifndef _PARANUT_
45 #define _PARANUT_
46 
47 #include "dm.h"
48 #include "exu.h"
49 #include "csr.h"
50 #include "ifu.h"
51 #include "intc.h"
52 #include "jtag_dtm.h"
53 #include "lsu.h"
54 #include "memu.h"
55 #include "mtimer.h"
56 
57 #include <systemc.h>
58 
59 
60 class MParanut : ::sc_core::sc_module {
61 public:
62  // Ports (WISHBONE master)...
63  sc_in<bool> clk_i; // clock input
64  sc_in<bool> rst_i; // reset
65 
66  sc_out<bool> cyc_o; // cycle valid output
67  sc_out<bool> stb_o; // strobe output
68  sc_out<bool> we_o; // indicates write transfer
69  sc_out<sc_uint<3> > cti_o; // cycle type identifier
70  sc_out<sc_uint<2> > bte_o; // burst type extension
71  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH/8> > sel_o; // byte select outputs
72  sc_in<bool> ack_i; // normal termination
73  sc_in<bool> err_i; // termination w/ error (presently unsupported)
74  sc_in<bool> rty_i; // termination w/ retry (presently unsupported)
75 
76  sc_out<sc_uint<32> > adr_o; // address bus outputs
77  sc_in<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dat_i; // input data bus
78  sc_out<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dat_o; // output data bus
79 
80  // External interrupt sources
81  sc_in<bool> ex_int[CFG_NUT_EX_INT];
82 
83  // JTAG TAP
84  sc_in<bool> tck;
85  sc_in<bool> tms;
86  sc_in<bool> tdi;
87  sc_out<bool> tdo;
88 
89  // Constructor/Destructor...
90  SC_HAS_PROCESS (MParanut);
91  MParanut (sc_module_name name)
92  : sc_module (name) {
93  InitSubmodules ();
95  }
97 
98  // Functions...
99  void Trace (sc_trace_file * tf, int levels = 1);
100  void DisplayStatistics (const int num = 0) { exu[num]->DisplayStatistics (); }
101 
102  bool IsHalted () { return exu[0]->IsHalted (); }
103 
104  // Processes...
105  void InterconnectMethod ();
106 
107  // Submodules...
117 
118  protected:
119  // Connecting signals...
120 
121  // MEMU: read ports (rp), write ports (wp)...
123  sc_signal<bool> rp_paging[2 * CFG_NUT_CPU_CORES];
124  sc_signal<sc_uint<4> > rp_bsel[2 * CFG_NUT_CPU_CORES];
125  sc_signal<bool> rp_ack[2 * CFG_NUT_CPU_CORES];
126  sc_signal<sc_uint<32> > rp_adr[2 * CFG_NUT_CPU_CORES];
127  sc_signal<sc_uint<32> > rp_data[2 * CFG_NUT_CPU_CORES];
128  sc_signal<bool> rp_ac_r[2 * CFG_NUT_CPU_CORES];
129  sc_signal<bool> rp_ac_x[2 * CFG_NUT_CPU_CORES];
130  sc_signal<bool> rp_ac_u[2 * CFG_NUT_CPU_CORES];
132 
134  sc_signal<bool> wp_paging[CFG_NUT_CPU_CORES];
135  sc_signal<sc_uint<4> > wp_bsel[CFG_NUT_CPU_CORES];
136  sc_signal<bool> wp_ack[CFG_NUT_CPU_CORES];
138  sc_signal<bool> wp_scond_ok[CFG_NUT_CPU_CORES];
139  sc_signal<sc_uint<3> > wp_cache_op[CFG_NUT_CPU_CORES];
140  sc_signal<sc_uint<32> > wp_adr[CFG_NUT_CPU_CORES];
141  sc_signal<sc_uint<32> > wp_data[CFG_NUT_CPU_CORES];
142  sc_signal<bool> wp_ac_w[CFG_NUT_CPU_CORES];
144 
145  sc_signal<bool> wb_ack;
146  sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > wb_dat;
147 
148  // IFU ...
151  ifu_reset[CFG_NUT_CPU_CORES]; // todo: remove ifu_reset for mode 1 only CoPUs
152  sc_signal<sc_uint<32> > ifu_jump_adr[CFG_NUT_CPU_CAP2_CORES]; // jump adress
155  ifu_npc[CFG_NUT_CPU_CAP2_CORES]; // expected to be registered (fast) outputs
157 
158  // LSU ...
163  sc_signal<sc_uint<3> > lsu_cache_op[CFG_NUT_CPU_CORES];
164 
167  sc_signal<sc_uint<2> > lsu_width[CFG_NUT_CPU_CORES]; // "00" = word, "01" = byte, "10" = half word
168  sc_signal<bool> lsu_exts[CFG_NUT_CPU_CORES];
169  sc_signal<sc_uint<32> > lsu_adr[CFG_NUT_CPU_CORES];
170  sc_signal<sc_uint<32> > lsu_rdata[CFG_NUT_CPU_CORES];
171  sc_signal<sc_uint<32> > lsu_wdata[CFG_NUT_CPU_CORES];
172 
173  // from CePU
174  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > m3_pnce;
175  sc_signal<sc_uint<2> > m3_priv_mode;
176  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > m3_pnlm;
177  sc_signal<sc_uint<32> > cepu_pnifadr;
178  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > m3_pnifadren;
179  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > m3_pnxsel;
180  // to CePU
181  sc_signal<bool> m3_ir_request;
182  sc_signal<sc_uint<5> > m3_ir_id;
183  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > m3_pnhaltreq;
184  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > m3_pnx;
185  sc_signal<bool> m3_ex_i;
186  // others...
188  sc_signal<bool> m3_ir_ack;
189  sc_signal<bool> m3_ir_enable;
190 
191  // NEU
192  sc_signal<bool> mtimer_ack_i;
193  sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > mtimer_dat_i;
194  sc_signal<bool> mtimer_ir_request;
195  sc_signal<bool> mtimer_irq_enable_in;
196  sc_signal<bool> csr_mtip_in;
197 
198  // EXU ...
199  sc_signal<bool> exu_haltreq[CFG_NUT_CPU_CORES];
200  sc_signal<bool> exu_enable[CFG_NUT_CPU_CORES];
202  sc_signal<bool> exu_linked[CFG_NUT_CPU_CORES];
203  sc_signal<bool> exu_ex_o[CFG_NUT_CPU_CORES];
204  sc_signal<bool> exu_xsel[CFG_NUT_CPU_CORES];
205  sc_signal<sc_uint<5> > exu_cause[CFG_NUT_CPU_CORES - 1];
206  sc_signal<bool> exu_sync[CFG_NUT_CPU_CORES];
207  sc_signal<bool> exu_dbg_req[CFG_NUT_CPU_CORES];
208 
209  // DM ...
210  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > dbg_req;
211  sc_signal<bool> dbg_reset;
212  // from DM
213  sc_signal<bool> dbg_ack_i;
214  sc_signal<sc_uint<CFG_MEMU_BUSIF_WIDTH> > dbg_dat_i;
215 
216  // DTM ...
217  sc_signal<sc_uint<DTM_ADDR_WIDTH> > dmi_adr; // address output
218  sc_signal<sc_uint<32> > dmi_dat_o; // output data
219  sc_signal<sc_uint<32> > dmi_dat_i; // input data
220  sc_signal<bool> dmi_rd, dmi_wr;
221 
222  // EXU-CSR
223  sc_signal<sc_uint<32> > csr_pc[CFG_NUT_CPU_CORES], csr_ir[CFG_NUT_CPU_CORES];
224  sc_signal<sc_uint<CFG_NUT_CPU_CORES_LD> > csr_hartID[CFG_NUT_CPU_CORES];
225  sc_signal<bool> csr_inCePU[CFG_NUT_CPU_CORES];
226  sc_signal<bool> csr_linked[CFG_NUT_CPU_CORES];
229  sc_signal<bool> csr_enable[CFG_NUT_CPU_CORES];
230  sc_signal<sc_uint<5> > ex_id_reg[CFG_NUT_CPU_CORES];
231  sc_signal<bool> sret_dreg[CFG_NUT_CPU_CORES];
232  sc_signal<bool> exception[CFG_NUT_CPU_CORES];
233  sc_signal<bool> irq_dreg[CFG_NUT_CPU_CORES];
235  sc_signal<sc_uint<5> > csr_rs1_reg[CFG_NUT_CPU_CORES];
236  sc_signal<sc_uint<32> > csr_op_a[CFG_NUT_CPU_CORES];
237  sc_signal<sc_uint<3> > csr_function_reg[CFG_NUT_CPU_CORES];
238  sc_signal<sc_uint<12> > csr_adr_reg[CFG_NUT_CPU_CORES];
239  sc_signal<sc_uint<32> > csr_tval[CFG_NUT_CPU_CORES];
240  sc_signal<sc_uint<CFG_NUT_CPU_CORES> >
244  sc_signal<sc_uint<2> > csr_m3_priv_mode[CFG_NUT_CPU_CORES];
245  sc_signal<bool>
248  sc_signal<bool> csr_isHalted[CFG_NUT_CPU_CORES];
249 
256  sc_signal<sc_uint<32> >
262 
264 
265  sc_signal<bool>
268 
269  sc_signal<sc_uint<32> >
275  sc_signal<sc_uint<5> > csr_cause[CFG_NUT_CPU_CORES];
276 
277  sc_signal<bool> csr_ack[CFG_NUT_CPU_CORES];
279 
280  sc_signal<sc_uint<CFG_NUT_CPU_CORES> > csr_m3_pnhaltreq[CFG_NUT_CPU_CORES], csr_m3_pnx[CFG_NUT_CPU_CORES];
281 
284  sc_signal<sc_uint<20> > root_ppn;
286  sc_signal<sc_uint<20> > csr_satp_root_ppn[CFG_NUT_CPU_CORES];
287 
288  sc_signal<bool> tlb_flush;
289 
290 
291 #if CFG_EXU_PERFCOUNT_ENABLE == 1
292  sc_signal<bool> perf_inc[CFG_NUT_CPU_CORES];
293  sc_signal<sc_uint<CFG_EXU_PERFCOUNTERS_LD> > perf_addr[CFG_NUT_CPU_CORES];
294 #endif
295 
296  // INTC ...
297  sc_signal<sc_uint<CFG_NUT_EX_INT> > intc_ex_int;
298  // INTC-CSR
299  sc_signal<bool> csr_mip_MTIP;
300  sc_signal<bool> csr_mip_MEIP;
301 
302  // ParaNut reset ...
303  sc_signal<bool> reset;
304 
305  // Methods...
306  void InitSubmodules ();
307  void FreeSubmodules ();
308  void InitInterconnectMethod ();
309 
310  // Helpers...
311 };
312 
313 
314 #endif
Definition: dm.h:133
Definition: jtag_dtm.h:119
Definition: exu.h:140
bool IsHalted()
Definition: exu.h:377
void DisplayStatistics()
Definition: exu.h:376
Definition: ifu.h:48
Definition: intc.h:51
Definition: lsu.h:86
Definition: memu.h:1111
Definition: nut.h:60
sc_signal< sc_uint< 32 > > cepu_pnifadr
Definition: nut.h:177
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnce[CFG_NUT_CPU_CORES]
Definition: nut.h:241
sc_signal< sc_uint< 32 > > csr_mideleg[CFG_NUT_CPU_CORES]
Definition: nut.h:259
sc_signal< bool > lsu_align_err[CFG_NUT_CPU_CORES]
Definition: nut.h:165
sc_signal< bool > perf_inc[CFG_NUT_CPU_CORES]
Definition: nut.h:292
sc_signal< sc_uint< 5 > > csr_cause[CFG_NUT_CPU_CORES]
Definition: nut.h:275
sc_signal< bool > m3_ir_request
Definition: nut.h:181
sc_signal< bool > exu_ex_o[CFG_NUT_CPU_CORES]
Definition: nut.h:203
sc_in< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_i
Definition: nut.h:77
sc_signal< sc_uint< 32 > > ifu_pc[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:154
sc_signal< sc_uint< 5 > > csr_rs1_reg[CFG_NUT_CPU_CORES]
Definition: nut.h:235
sc_signal< bool > dbg_reset
Definition: nut.h:211
sc_signal< bool > csr_mstatus_TSR[CFG_NUT_CPU_CORES]
Definition: nut.h:253
sc_out< bool > cyc_o
Definition: nut.h:66
sc_signal< bool > lsu_exts[CFG_NUT_CPU_CORES]
Definition: nut.h:168
sc_out< bool > we_o
Definition: nut.h:68
sc_signal< bool > m3_dcache_enable
Definition: nut.h:187
~MParanut()
Definition: nut.h:96
sc_signal< bool > rp_ac_x[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:129
sc_out< bool > stb_o
Definition: nut.h:67
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnhaltreq[CFG_NUT_CPU_CORES]
Definition: nut.h:280
MIfu * ifu[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:112
sc_signal< sc_uint< 5 > > ex_id_reg[CFG_NUT_CPU_CORES]
Definition: nut.h:230
sc_signal< bool > lsu_lres_scond[CFG_NUT_CPU_CORES]
Definition: nut.h:162
sc_signal< sc_uint< 32 > > csr_rdata[CFG_NUT_CPU_CORES]
Definition: nut.h:274
MDtm * dtm
Definition: nut.h:110
sc_signal< sc_uint< 32 > > csr_op_a[CFG_NUT_CPU_CORES]
Definition: nut.h:236
sc_signal< bool > csr_mip_MTIP
Definition: nut.h:299
sc_signal< bool > wp_paging[CFG_NUT_CPU_CORES]
Definition: nut.h:134
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnifadren
Definition: nut.h:178
sc_signal< sc_uint< 32 > > csr_tval[CFG_NUT_CPU_CORES]
Definition: nut.h:239
sc_signal< bool > csr_ifu_paging_mode[CFG_NUT_CPU_CORES]
Definition: nut.h:282
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > mtimer_dat_i
Definition: nut.h:193
sc_signal< sc_uint< CFG_NUT_CPU_CORES_LD > > csr_hartID[CFG_NUT_CPU_CORES]
Definition: nut.h:224
sc_signal< sc_uint< 32 > > rp_data[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:127
sc_signal< bool > exu_ifu_reset[CFG_NUT_CPU_CORES]
Definition: nut.h:201
sc_signal< sc_uint< 32 > > csr_mtvec[CFG_NUT_CPU_CORES]
Definition: nut.h:272
sc_signal< bool > ifu_reset[CFG_NUT_CPU_CORES]
Definition: nut.h:151
sc_signal< sc_uint< DTM_ADDR_WIDTH > > dmi_adr
Definition: nut.h:217
sc_signal< bool > irq_dreg[CFG_NUT_CPU_CORES]
Definition: nut.h:233
sc_signal< bool > wp_trap_no_u[CFG_NUT_CPU_CORES]
Definition: nut.h:143
sc_out< sc_uint< 32 > > adr_o
Definition: nut.h:76
sc_signal< bool > m3_ir_enable
Definition: nut.h:189
sc_signal< bool > lsu_wr[CFG_NUT_CPU_CORES]
Definition: nut.h:159
sc_signal< bool > exu_haltreq[CFG_NUT_CPU_CORES]
Definition: nut.h:199
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnxsel
Definition: nut.h:179
sc_signal< sc_uint< 2 > > load_store_priv_mode[CFG_NUT_CPU_CORES]
Definition: nut.h:250
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnlm
Definition: nut.h:176
sc_signal< bool > csr_lsu_paging_mode[CFG_NUT_CPU_CORES]
Definition: nut.h:282
sc_in< bool > ack_i
Definition: nut.h:72
sc_signal< sc_uint< 20 > > root_ppn
Definition: nut.h:284
sc_signal< sc_uint< 2 > > m3_priv_mode
Definition: nut.h:175
sc_signal< bool > csr_ack[CFG_NUT_CPU_CORES]
Definition: nut.h:277
MExu * exu[CFG_NUT_CPU_CORES]
Definition: nut.h:114
sc_in< bool > tck
Definition: nut.h:84
sc_signal< sc_uint< 5 > > m3_ir_id
Definition: nut.h:182
sc_signal< bool > ifu_next[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:149
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnce
Definition: nut.h:174
sc_signal< bool > ifu_paging_mode
Definition: nut.h:283
sc_signal< bool > wp_wr[CFG_NUT_CPU_CORES]
Definition: nut.h:133
sc_signal< sc_uint< 32 > > csr_stvec[CFG_NUT_CPU_CORES]
Definition: nut.h:258
sc_signal< bool > lsu_paging_mode
Definition: nut.h:283
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnxsel[CFG_NUT_CPU_CORES]
Definition: nut.h:243
void InitSubmodules()
Definition: nut.cpp:133
sc_signal< bool > csr_linked[CFG_NUT_CPU_CORES]
Definition: nut.h:226
sc_signal< bool > csr_m3_icache_enable[CFG_NUT_CPU_CORES]
Definition: nut.h:246
sc_signal< bool > ifu_ac_x[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:156
sc_signal< bool > csr_mtip_in
Definition: nut.h:196
sc_signal< sc_uint< 32 > > csr_dpc[CFG_NUT_CPU_CORES]
Definition: nut.h:271
sc_signal< bool > csr_cache_flush[CFG_NUT_CPU_CORES]
Definition: nut.h:278
sc_signal< bool > ifu_flush[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:150
sc_signal< bool > exception[CFG_NUT_CPU_CORES]
Definition: nut.h:232
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > wb_dat
Definition: nut.h:146
sc_signal< sc_uint< 32 > > wp_data[CFG_NUT_CPU_CORES]
Definition: nut.h:141
sc_signal< bool > pop_priv_ir_stack_dreg[CFG_NUT_CPU_CORES]
Definition: nut.h:234
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dat_o
Definition: nut.h:78
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > dbg_req
Definition: nut.h:210
sc_signal< bool > csr_mstatus_MIE[CFG_NUT_CPU_CORES]
Definition: nut.h:251
sc_signal< sc_uint< 4 > > wp_bsel[CFG_NUT_CPU_CORES]
Definition: nut.h:135
sc_signal< bool > wp_ack[CFG_NUT_CPU_CORES]
Definition: nut.h:136
sc_signal< bool > csr_dcsr_step[CFG_NUT_CPU_CORES]
Definition: nut.h:266
sc_signal< sc_uint< 32 > > csr_mip[CFG_NUT_CPU_CORES]
Definition: nut.h:260
sc_signal< sc_uint< 32 > > dmi_dat_i
Definition: nut.h:219
void InterconnectMethod()
Definition: nut.cpp:872
sc_signal< bool > mtimer_ack_i
Definition: nut.h:192
sc_signal< bool > dmi_wr
Definition: nut.h:220
sc_signal< bool > lsu_rd[CFG_NUT_CPU_CORES]
Definition: nut.h:159
sc_signal< bool > dmi_rd
Definition: nut.h:220
sc_signal< bool > rp_rd[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:122
sc_signal< bool > ifu_ac_u[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:156
MParanut(sc_module_name name)
Definition: nut.h:91
sc_signal< bool > exu_enable[CFG_NUT_CPU_CORES]
Definition: nut.h:200
sc_signal< sc_uint< 32 > > dmi_dat_o
Definition: nut.h:218
sc_signal< bool > wp_scond_ok[CFG_NUT_CPU_CORES]
Definition: nut.h:138
sc_signal< bool > m3_icache_enable
Definition: nut.h:187
void InitInterconnectMethod()
Definition: nut.cpp:856
sc_signal< bool > dbg_enter_dreg[CFG_NUT_CPU_CORES]
Definition: nut.h:228
MIntC * intc
Definition: nut.h:111
sc_out< sc_uint< 2 > > bte_o
Definition: nut.h:70
sc_signal< bool > delegate_dreg[CFG_NUT_CPU_CORES]
Definition: nut.h:261
sc_signal< bool > csr_satp_mode[CFG_NUT_CPU_CORES]
Definition: nut.h:285
sc_signal< bool > rp_ac_r[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:128
sc_signal< sc_uint< 32 > > lsu_wdata[CFG_NUT_CPU_CORES]
Definition: nut.h:171
sc_signal< bool > lsu_ac_u[CFG_NUT_CPU_CORES]
Definition: nut.h:161
sc_signal< bool > mtimer_irq_enable_in
Definition: nut.h:195
sc_signal< sc_uint< 2 > > csr_m3_priv_mode[CFG_NUT_CPU_CORES]
Definition: nut.h:244
sc_signal< bool > wb_ack
Definition: nut.h:145
sc_signal< bool > lsu_ac_r[CFG_NUT_CPU_CORES]
Definition: nut.h:161
sc_signal< bool > exu_dbg_req[CFG_NUT_CPU_CORES]
Definition: nut.h:207
sc_signal< bool > rp_paging[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:123
MLsu * lsu[CFG_NUT_CPU_CORES]
Definition: nut.h:115
sc_signal< bool > csr_mstatus_SIE[CFG_NUT_CPU_CORES]
Definition: nut.h:252
sc_signal< sc_uint< 3 > > wp_cache_op[CFG_NUT_CPU_CORES]
Definition: nut.h:139
sc_in< bool > clk_i
Definition: nut.h:63
sc_signal< sc_uint< 32 > > wp_adr[CFG_NUT_CPU_CORES]
Definition: nut.h:140
sc_signal< sc_uint< 32 > > ifu_jump_adr[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:152
sc_signal< sc_uint< 32 > > lsu_rdata[CFG_NUT_CPU_CORES]
Definition: nut.h:170
sc_out< sc_uint< 3 > > cti_o
Definition: nut.h:69
sc_signal< bool > sret_dreg[CFG_NUT_CPU_CORES]
Definition: nut.h:231
sc_signal< bool > wp_lres_scond[CFG_NUT_CPU_CORES]
Definition: nut.h:137
sc_signal< sc_uint< CFG_MEMU_BUSIF_WIDTH > > dbg_dat_i
Definition: nut.h:214
sc_signal< sc_uint< 12 > > csr_adr_reg[CFG_NUT_CPU_CORES]
Definition: nut.h:238
Mtimer * mtimer
Definition: nut.h:116
sc_signal< bool > wp_trap_u[CFG_NUT_CPU_CORES]
Definition: nut.h:143
sc_signal< bool > lsu_trap_no_u[CFG_NUT_CPU_CORES]
Definition: nut.h:160
sc_signal< bool > csr_enable[CFG_NUT_CPU_CORES]
Definition: nut.h:229
sc_signal< bool > m3_ir_ack
Definition: nut.h:188
sc_signal< bool > rp_ac_u[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:130
sc_signal< bool > ifu_ir_valid[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:153
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnx
Definition: nut.h:184
sc_signal< sc_uint< 3 > > lsu_cache_op[CFG_NUT_CPU_CORES]
Definition: nut.h:163
sc_signal< sc_uint< 32 > > ifu_ir[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:154
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnx[CFG_NUT_CPU_CORES]
Definition: nut.h:280
sc_in< bool > rty_i
Definition: nut.h:74
void FreeSubmodules()
Definition: nut.cpp:839
sc_signal< sc_uint< 4 > > rp_bsel[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:124
sc_signal< sc_uint< 32 > > csr_mepc[CFG_NUT_CPU_CORES]
Definition: nut.h:270
void Trace(sc_trace_file *tf, int levels=1)
Definition: nut.cpp:44
sc_signal< bool > rp_trap_no_u[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:131
sc_signal< bool > lsu_ac_w[CFG_NUT_CPU_CORES]
Definition: nut.h:161
sc_signal< bool > rp_direct[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:122
sc_signal< sc_uint< 32 > > csr_mcause[CFG_NUT_CPU_CORES]
Definition: nut.h:273
MCsr * csr[CFG_NUT_CPU_CORES]
Definition: nut.h:113
MDebugModule * dm
Definition: nut.h:109
sc_signal< bool > wp_ac_w[CFG_NUT_CPU_CORES]
Definition: nut.h:142
sc_in< bool > tms
Definition: nut.h:85
sc_signal< sc_uint< CFG_EXU_PERFCOUNTERS_LD > > perf_addr[CFG_NUT_CPU_CORES]
Definition: nut.h:293
sc_signal< bool > ifu_jump[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:149
sc_signal< sc_uint< 2 > > priv_mode[CFG_NUT_CPU_CORES]
Definition: nut.h:250
sc_signal< bool > csr_inCePU[CFG_NUT_CPU_CORES]
Definition: nut.h:225
sc_signal< bool > exu_linked[CFG_NUT_CPU_CORES]
Definition: nut.h:202
MMemu * memu
Definition: nut.h:108
sc_signal< bool > csr_mstatus_TVM[CFG_NUT_CPU_CORES]
Definition: nut.h:255
sc_signal< bool > csr_exception[CFG_NUT_CPU_CORES]
Definition: nut.h:263
sc_signal< sc_uint< 32 > > ifu_npc[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:155
sc_signal< bool > exu_xsel[CFG_NUT_CPU_CORES]
Definition: nut.h:204
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > csr_m3_pnlm[CFG_NUT_CPU_CORES]
Definition: nut.h:242
sc_signal< bool > dbg_reg[CFG_NUT_CPU_CORES]
Definition: nut.h:228
sc_signal< bool > lsu_scond_ok[CFG_NUT_CPU_CORES]
Definition: nut.h:166
sc_signal< bool > lsu_trap_u[CFG_NUT_CPU_CORES]
Definition: nut.h:160
sc_signal< bool > dbg[CFG_NUT_CPU_CORES]
Definition: nut.h:228
sc_signal< sc_uint< 32 > > csr_ir[CFG_NUT_CPU_CORES]
Definition: nut.h:223
sc_signal< bool > dbg_ack_i
Definition: nut.h:213
sc_signal< sc_uint< 20 > > csr_satp_root_ppn[CFG_NUT_CPU_CORES]
Definition: nut.h:286
sc_signal< bool > csr_mip_MEIP
Definition: nut.h:300
sc_signal< bool > csr_cpu_enabled[CFG_NUT_CPU_CORES]
Definition: nut.h:227
sc_signal< sc_uint< 5 > > exu_cause[CFG_NUT_CPU_CORES - 1]
Definition: nut.h:205
sc_in< bool > err_i
Definition: nut.h:73
sc_signal< bool > wp_direct[CFG_NUT_CPU_CORES]
Definition: nut.h:133
sc_signal< sc_uint< 32 > > csr_sepc[CFG_NUT_CPU_CORES]
Definition: nut.h:257
sc_signal< sc_uint< 32 > > lsu_adr[CFG_NUT_CPU_CORES]
Definition: nut.h:169
sc_signal< bool > csr_mstatus_SUM[CFG_NUT_CPU_CORES]
Definition: nut.h:254
sc_out< bool > tdo
Definition: nut.h:87
sc_out< sc_uint< CFG_MEMU_BUSIF_WIDTH/8 > > sel_o
Definition: nut.h:71
sc_signal< sc_uint< CFG_NUT_CPU_CORES > > m3_pnhaltreq
Definition: nut.h:183
sc_signal< bool > m3_ex_i
Definition: nut.h:185
sc_signal< bool > exu_sync[CFG_NUT_CPU_CORES]
Definition: nut.h:206
sc_signal< bool > rp_trap_u[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:131
sc_signal< bool > csr_isHalted[CFG_NUT_CPU_CORES]
Definition: nut.h:248
sc_signal< sc_uint< 3 > > csr_function_reg[CFG_NUT_CPU_CORES]
Definition: nut.h:237
sc_signal< sc_uint< 32 > > csr_pc[CFG_NUT_CPU_CORES]
Definition: nut.h:223
sc_in< bool > ex_int[CFG_NUT_EX_INT]
Definition: nut.h:81
sc_signal< bool > rp_ack[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:125
sc_signal< bool > csr_dcsr_ebreakm[CFG_NUT_CPU_CORES]
Definition: nut.h:267
sc_signal< bool > lsu_ack[CFG_NUT_CPU_CORES]
Definition: nut.h:165
sc_signal< bool > tlb_flush
Definition: nut.h:288
sc_in< bool > tdi
Definition: nut.h:86
sc_signal< bool > csr_m3_dcache_enable[CFG_NUT_CPU_CORES]
Definition: nut.h:247
void DisplayStatistics(const int num=0)
Definition: nut.h:100
sc_signal< sc_uint< 2 > > lsu_width[CFG_NUT_CPU_CORES]
Definition: nut.h:167
sc_signal< bool > ifu_npc_valid[CFG_NUT_CPU_CAP2_CORES]
Definition: nut.h:153
sc_signal< sc_uint< CFG_NUT_EX_INT > > intc_ex_int
Definition: nut.h:297
bool IsHalted()
Definition: nut.h:102
sc_signal< bool > reset
Definition: nut.h:303
sc_in< bool > rst_i
Definition: nut.h:64
sc_signal< bool > lsu_flush[CFG_NUT_CPU_CORES]
Definition: nut.h:159
sc_signal< sc_uint< 32 > > rp_adr[2 *CFG_NUT_CPU_CORES]
Definition: nut.h:126
sc_signal< bool > mtimer_ir_request
Definition: nut.h:194
Definition: mtimer.h:53
#define CFG_NUT_EX_INT
Number of external interrupt lines.
Definition: paranut-config.h:125
#define CFG_NUT_CPU_CAP2_CORES
Number of cores (ExUs) with mode capability >= 2 (thread) (derived).
Definition: paranut-config.h:110
#define CFG_NUT_CPU_CORES
Number of cores overall (derived).
Definition: paranut-config.h:98
#define CFG_MEMU_BUSIF_WIDTH
Busif Data Width.
Definition: paranut-config.h:228
sc_trace_file * tf
Definition: tlb_tb.cpp:94