ParaNut SystemC Model
A SystemC Model of the ParaNut architecture
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Memory Unit options. More...
Memory Unit options... | |
#define | CFG_MEMU_CACHE_BANKS_LD 2 |
Number of cache banks as log2. More... | |
#define | CFG_MEMU_CACHE_BANKS (1 << CFG_MEMU_CACHE_BANKS_LD) |
Number of cache banks (derived). More... | |
#define | CFG_MEMU_CACHE_SETS_LD 9 |
Number of cache sets as log2. More... | |
#define | CFG_MEMU_CACHE_SETS (1 << CFG_MEMU_CACHE_SETS_LD) |
Number of cache sets (derived). More... | |
#define | CFG_MEMU_CACHE_WAYS_LD 2 |
Number of cache ways as log2. More... | |
#define | CFG_MEMU_CACHE_WAYS (1 << CFG_MEMU_CACHE_WAYS_LD) |
Number of cache ways (derived). More... | |
#define | CFG_MEMU_BANK_RAM_PORTS 2 |
Number of ports per bank. More... | |
#define | CFG_MEMU_CACHE_REPLACE_LRU 1 |
Cache replacement method. More... | |
#define | CFG_MEMU_ARBITER_METHOD 7 |
Arbiter Method. More... | |
#define | CFG_MEMU_BUSIF_WIDTH 32 |
Busif Data Width. More... | |
#define | CFG_MEMU_CACHE_SIZE (CFG_MEMU_CACHE_SETS * CFG_MEMU_CACHE_WAYS * CFG_MEMU_CACHE_BANKS * 4) |
Overall cache size in Bytes (derived). More... | |
#define | CFG_MEMU_WPORTS CFG_NUT_CPU_CORES |
Number of write ports (WPORTS) in the MemU (derived). More... | |
#define | CFG_MEMU_RPORTS (2 * CFG_NUT_CPU_CORES) |
Number of read ports (RPORTS) in the MemU (derived). More... | |
Memory Unit options.
#define CFG_MEMU_ARBITER_METHOD 7 |
Arbiter Method.
Defines the MemU arbitration method/strategy, either a round-robin or pseudo-random arbitration.
>0 | - round-robin arbitration, switches every (1 << CFG_MEMU_ARBITER_METHOD) clocks |
<0 | - pseudo-random arbitration (LFSR-based) |
#define CFG_MEMU_BANK_RAM_PORTS 2 |
Number of ports per bank.
Since every bank is implemented as one Block RAM, for maximum performance this should be set to the maximum number of Block RAM ports supported by the target device (i.e. 2) but can be reduced in order to save some area.
#define CFG_MEMU_BUSIF_WIDTH 32 |
Busif Data Width.
Defines the width of the master Wishbone data bus.
32 | - 32 Bit data width |
64 | - 64 Bit data width |
#define CFG_MEMU_CACHE_BANKS (1 << CFG_MEMU_CACHE_BANKS_LD) |
Number of cache banks (derived).
#define CFG_MEMU_CACHE_BANKS_LD 2 |
Number of cache banks as log2.
Defines the log2 of the number of cache banks. A cache line has a size of CFG_MEMU_CACHE_BANKS words. A good starting point is 2 (4 banks).
#define CFG_MEMU_CACHE_REPLACE_LRU 1 |
Cache replacement method.
Defines the cache replacement method/strategy, either pseudo-random or least recently used (LRU).
0 | - random replacement |
1 | - LRU replacement |
#define CFG_MEMU_CACHE_SETS (1 << CFG_MEMU_CACHE_SETS_LD) |
Number of cache sets (derived).
#define CFG_MEMU_CACHE_SETS_LD 9 |
Number of cache sets as log2.
Defines the log2 of the number of cache sets. A bank has CFG_MEMU_CACHE_SETS * CFG_MEMU_CACHE_WAYS words.
#define CFG_MEMU_CACHE_SIZE (CFG_MEMU_CACHE_SETS * CFG_MEMU_CACHE_WAYS * CFG_MEMU_CACHE_BANKS * 4) |
Overall cache size in Bytes (derived).
#define CFG_MEMU_CACHE_WAYS (1 << CFG_MEMU_CACHE_WAYS_LD) |
Number of cache ways (derived).
#define CFG_MEMU_CACHE_WAYS_LD 2 |
Number of cache ways as log2.
Defines the log2 of the number of cache ways (cache associativity). A bank has CFG_MEMU_CACHE_SETS * CFG_MEMU_CACHE_WAYS words.
0 | - 1-way set-associativity |
1 | - 2-way set-associativity |
2 | - 4-way set-associativity |
#define CFG_MEMU_RPORTS (2 * CFG_NUT_CPU_CORES) |
Number of read ports (RPORTS) in the MemU (derived).
#define CFG_MEMU_WPORTS CFG_NUT_CPU_CORES |
Number of write ports (WPORTS) in the MemU (derived).