NGW/NGW100 Clock system

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Overview

The AP7000 processor on NGW100 has three clock sources: Two crystals XC0 and XC1 operating at 20 and 12 MHz respectively, and a 32 Khz slow clock crystal, XC3 to source real time clocks.

Different modules in AP7000 can be configured to be driven directly from XC0, XC1 or an up-sampled clock provided by PLL modules in AP7000.

The PLL modules PLL0 and PLL1 are driven by XC0 and XC1 respectively. Their output is filtered which are tuned for the maximum and minimum frequency of the Network Gateway.

PLL filter schematic

Image:NGW100PLLFilterSch.gif

Filter values

Default settings of the two PLL filters are tuned for the use listed below. Please refer the AP7000 datasheet for a description of the PLL's in AP7000.

FilterFoscDIVMULFn (PLL bandwidth)FoutR17/R18C6/C7C14/C15
PLL020MHz21330kHz130MHzR18=430RC7=1.8nFC14=18nF
PLL120MHz41630kHz80MHzR17=150RC6=5.6nFC15=56nF

The output frequency is calculated as follows:

Fout = (Fosc / DIV) * MUL
Static version created: 2007-03-07
Copyright (c) 2007 Atmel Corporation